
/****************************************************************************************************//**
 * @file     me32g030.h
 *
 * @brief    CMSIS Cortex-M0 Peripheral Access Layer Header File for
 *           me32g030 from .
 *
 * @version  V1.0
 * @date     27. November 2020
 *
 * @note     Generated with SVDConv V2.86d 
 *           from CMSIS SVD File 'me32g030.svd' Version 1.0,
 *******************************************************************************************************/



/** @addtogroup (null)
  * @{
  */

/** @addtogroup me32g030
  * @{
  */

#ifndef ME32G030_H
#define ME32G030_H

#ifdef __cplusplus
extern "C" {
#endif


/* -------------------------  Interrupt Number Definition  ------------------------ */

typedef enum {
/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
/* ---------------------  me32g030 Specific Interrupt Numbers  -------------------- */
  WDT_IRQn                      =   0,              /*!<   0  WDT interrupt                                                    */
  BOD_IRQn                      =   1,              /*!<   1  BOD interrupt                                                    */
  PWMFAULT_IRQn                 =   2,              /*!<   2  PWM fault interrupt                                              */
  PA_IRQn                       =   3,              /*!<   3  PA interrupt                                                     */
  PB_IRQn                       =   4,              /*!<   4  PB interrupt                                                     */
  PC_IRQn                       =   5,              /*!<   5  PC interrupt                                                     */
  DMA_IRQn                      =   6,              /*!<   6  DMA interrupt                                                    */
  BTIM0_IRQn                    =   7,              /*!<   7  Basic TIM0 interrupt                                             */
  BTIM1_IRQn                    =   8,              /*!<   8  Basic TIM1 interrupt                                             */
  BTIM2_IRQn                    =   9,              /*!<   9  Basic TIM2 interrupt                                             */
  BTIM3_IRQn                    =  10,              /*!<  10  Basic TIM3 interrupt                                             */
  CTIM0_IRQn                    =  11,              /*!<  11  Advance TIM0 interrupt                                           */
  CTIM1_IRQn                    =  12,              /*!<  12  Advance TIM1 interrupt                                           */
  ADC_IRQn                      =  13,              /*!<  13  ADC interrupt                                                    */
  I2C0_IRQn                     =  14,              /*!<  14  I2C0 interrupt                                                   */
  I2C1_IRQn                     =  15,              /*!<  15  I2C1 interrupt                                                   */
  SPI0_IRQn                     =  16,              /*!<  16  SPI0 interrupt                                                   */
  SPI1_IRQn                     =  17,              /*!<  17  SPI1 interrupt                                                   */
  PWM_IRQn                      =  18,              /*!<  18  PWM Event interrupt                                              */
  UART0_IRQn                    =  19,              /*!<  19  UART0 interrupt                                                  */
  UART1_IRQn                    =  20,              /*!<  20  UART1 interrupt                                                  */
  UART2_IRQn                    =  21,              /*!<  21  UART2 interrupt                                                  */
  UART3_IRQn                    =  22,              /*!<  22  UART3 interrupt                                                  */
  ACMP0_IRQn                    =  23,              /*!<  23  ACMP0 interrupt                                                  */
  ACMP1_IRQn                    =  24,              /*!<  24  ACMP1 interrupt                                                  */
  RTC_IRQn                      =  25               /*!<  25  RTC interrupt                                                    */
} IRQn_Type;


/** @addtogroup Configuration_of_CMSIS
  * @{
  */


/* ================================================================================ */
/* ================      Processor and Core Peripheral Section     ================ */
/* ================================================================================ */

/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
#define __CM0_REV                 0x0000            /*!< Cortex-M0 Core Revision                                               */
#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0.h"                               /*!< Cortex-M0 processor and core peripherals                              */
#include "system_me32g030.h"                        /*!< me32g030 System                                                       */


/* ================================================================================ */
/* ================       Device Specific Peripheral Section       ================ */
/* ================================================================================ */


/** @addtogroup Device_Peripheral_Registers
  * @{
  */


/* -------------------  Start of section using anonymous unions  ------------------ */
#if defined(__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined(__ICCARM__)
  #pragma language=extended
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
  #pragma warning 586
#else
  #warning Not supported compiler type
#endif



/* ================================================================================ */
/* ================                       DIA                      ================ */
/* ================================================================================ */


/**
  * @brief Device information array (DIA)
  */

typedef struct {                                    /*!< DIA Structure                                                         */
  __I  uint32_t  DID;                               /*!< Device ID                                                             */
  __I  uint32_t  VERID;                             /*!< Hardware version                                                      */
  __I  uint32_t  UNIQUEID0;                         /*!< Unique device serial no- low 32-bit                                   */
  __I  uint32_t  UNIQUEID1;                         /*!< Unique device serial no- high 32-bit                                  */
  __I  uint32_t  IRCTRIM;                           /*!< Internal IRC 40M trim value                                           */
  __I  uint32_t  IRCFREQ;                           /*!< Internal IRC value                                                    */
  __I  uint32_t  VREF;                              /*!< Internal ADC Vref value                                               */
  __I  uint32_t  RESERVED[118];
  
  union {
    __I  uint32_t  PROTECTION;                      /*!< Chip protection setting                                               */
    
    struct {
      __I  uint32_t  NVR7_LOCK  : 28;               /*!< Lock NVR 7th when value equals 0x84A6C57                              */
           uint32_t             :  2;
      __I  uint32_t  SWD_EN     :  1;               /*!< SWD Enable                                                            */
      __I  uint32_t  NVR_WRITE_EN:  1;              /*!< NVR write enable                                                      */
    } PROTECTION_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  CHIPCFG;                         /*!< Chip configragtion                                                    */
    
    struct {
      __I  uint32_t  FLASHCFG   :  2;               /*!< Config flash size as 64/48/32/16K                                     */
    } CHIPCFG_b;                                    /*!< BitSize                                                               */
  };
  __I  uint32_t  MARK;                              /*!< virgin mark 0x55AAAA55                                                */
} DIA_Type;


/* ================================================================================ */
/* ================                     SYSCON                     ================ */
/* ================================================================================ */


/**
  * @brief System control register (SYSCON)
  */

typedef struct {                                    /*!< SYSCON Structure                                                      */
  
  union {
    __IO uint32_t  SYSMEMREMAP;                     /*!< System memory remap register                                          */
    
    struct {
      __IO uint32_t  MAP        :  2;               /*!< System memory remap                                                   */
    } SYSMEMREMAP_b;                                /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PRESETCTRL;                      /*!< Peripheral reset control register                                     */
    
    struct {
      __IO uint32_t  I2C0_RST_N :  1;               /*!< I2C0 reset control                                                    */
      __IO uint32_t  I2C1_RST_N :  1;               /*!< I2C1 reset control                                                    */
      __IO uint32_t  SPI0_RST_N :  1;               /*!< SPI0 reset control                                                    */
      __IO uint32_t  SPI1_RST_N :  1;               /*!< SPI1 reset control                                                    */
      __IO uint32_t  UART0_RST_N:  1;               /*!< UART0 reset control                                                   */
      __IO uint32_t  UART1_RST_N:  1;               /*!< UART1 reset control                                                   */
      __IO uint32_t  UART2_RST_N:  1;               /*!< UART2 reset control                                                   */
      __IO uint32_t  UART3_RST_N:  1;               /*!< UART3 reset control                                                   */
      __IO uint32_t  BTIM0_RST_N:  1;               /*!< 16 bits basic counter/timer 0 (BTIM0) reset control                   */
      __IO uint32_t  BTIM1_RST_N:  1;               /*!< 16 bits basic counter/timer 1 (BTIM1) reset control                   */
      __IO uint32_t  BTIM2_RST_N:  1;               /*!< 16 bits basic counter/timer 2 (BTIM2) reset control                   */
      __IO uint32_t  BTIM3_RST_N:  1;               /*!< 16 bits basic counter/timer 3 (BTIM3) reset control                   */
      __IO uint32_t  CTIM0_RST_N:  1;               /*!< 16-bit advance counter/timer (CTIM0) reset control                    */
      __IO uint32_t  CTIM1_RST_N:  1;               /*!< 16-bit advance counter/timer (CTIM1) reset control                    */
      __IO uint32_t  ADC_RST_N  :  1;               /*!< ADC reset control                                                     */
      __IO uint32_t  CMP_RST_N  :  1;               /*!< Comparator reset control                                              */
      __IO uint32_t  PWM_RST_N  :  1;               /*!< 16-bit PWM counter/timer 1 (PWMCT) reset control                      */
      __IO uint32_t  CRC_RST_N  :  1;               /*!< CRC reset control                                                     */
      __IO uint32_t  DMA_RST_N  :  1;               /*!< DMA reset control                                                     */
    } PRESETCTRL_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  WAKEUPCTRL;                      /*!< Wake up control register                                              */
    
    struct {
      __IO uint32_t  WAKEUP0    :  1;               /*!< WAKEUP0 enable control                                                */
      __IO uint32_t  WAKEUP1    :  1;               /*!< WAKEUP1 enable control                                                */
      __IO uint32_t  WAKEUP2    :  1;               /*!< WAKEUP3 enable control                                                */
      __IO uint32_t  WAKEUP3    :  1;               /*!< WAKEUP3 enable control                                                */
    } WAKEUPCTRL_b;                                 /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED[6];
  
  union {
    __IO uint32_t  WDTOSCCTRL;                      /*!< WDT oscillator control register                                       */
    
    struct {
      __IO uint32_t  DIVSEL     :  5;               /*!< Select divider for Fclkana                                            */
      __IO uint32_t  TRIM       :  7;               /*!< Trim watchdog oscillator capacitor                                    */
      __IO uint32_t  WDTCLKSRC  :  1;               /*!< Watch dog timer clock source                                          */
    } WDTOSCCTRL_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  IRCCTRL;                         /*!< Internal RC oscillator control register                               */
    
    struct {
      __IO uint32_t  TRIM       :  8;               /*!< Trim value                                                            */
    } IRCCTRL_b;                                    /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED1[17];
  
  union {
    __IO uint32_t  MAINCLKSEL;                      /*!< Main clock source select register                                     */
    
    struct {
      __IO uint32_t  RTCSEL     :  1;               /*!< Clock source for RTC counter                                          */
      __IO uint32_t  MAINSEL    :  1;               /*!< Clock source for main clock                                           */
    } MAINCLKSEL_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MAINCLKUEN;                      /*!< Main clock source update enable register                              */
    
    struct {
      __IO uint32_t  ENA        :  1;               /*!< Enable main clock source update                                       */
    } MAINCLKUEN_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  SYSAHBCLKDIV;                    /*!< System AHB clock divider register                                     */
    
    struct {
      __IO uint32_t  DIV        :  8;               /*!< System AHB clock divider value                                        */
    } SYSAHBCLKDIV_b;                               /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED2;
  
  union {
    __IO uint32_t  SYSAHBCLKCTRL;                   /*!< AHB clock control register                                            */
    
    struct {
      __IO uint32_t  RAM        :  1;               /*!< Enables clock for SRAM                                                */
      __IO uint32_t  FLASHCTRL  :  1;               /*!< Enables clock for flash program controler                             */
      __IO uint32_t  FLASH      :  1;               /*!< Enables clock for flash access controler                              */
      __IO uint32_t  CRC_CLK    :  1;               /*!< Enables clock for CRC                                                 */
      __IO uint32_t  IOCON_CLK  :  1;               /*!< Enables clock for IO configuration block                              */
      __IO uint32_t  PWM_CLK    :  1;               /*!< Enables clock for 16-bit PWM timer                                    */
      __IO uint32_t  I2C0_CLK   :  1;               /*!< Enables clock for I2C0                                                */
      __IO uint32_t  I2C1_CLK   :  1;               /*!< Enables clock for I2C1                                                */
      __IO uint32_t  SPI0_CLK   :  1;               /*!< Enables clock for SPI0                                                */
      __IO uint32_t  SPI1_CLK   :  1;               /*!< Enables clock for SPI1                                                */
      __IO uint32_t  UART0_CLK  :  1;               /*!< Enables clock for UART0                                               */
      __IO uint32_t  UART1_CLK  :  1;               /*!< Enables clock for UART1                                               */
      __IO uint32_t  UART2_CLK  :  1;               /*!< Enables clock for UART2                                               */
      __IO uint32_t  UART3_CLK  :  1;               /*!< Enables clock for UART3                                               */
      __IO uint32_t  BTIM0_CLK  :  1;               /*!< Enables clock for 16-bit basement counter/timer 0                     */
      __IO uint32_t  BTIM1_CLK  :  1;               /*!< Enables clock for 16-bit basement counter/timer 1                     */
      __IO uint32_t  BTIM2_CLK  :  1;               /*!< Enables clock for 16-bit basement counter/timer 2                     */
      __IO uint32_t  BTIM3_CLK  :  1;               /*!< Enables clock for 16-bit basement counter/timer 3                     */
      __IO uint32_t  CTIM0_CLK  :  1;               /*!< Enables clock for 16-bit advsnced counter/timer 0                     */
      __IO uint32_t  CTIM1_CLK  :  1;               /*!< Enables clock for 16-bit advsnced counter/timer 1                     */
      __IO uint32_t  ADC_CLK    :  1;               /*!< Enables clock for ADC                                                 */
      __IO uint32_t  CMP_CLK    :  1;               /*!< Enables clock for CMP                                                 */
      __IO uint32_t  WDT_CLK    :  1;               /*!< Enables clock for WDT                                                 */
      __IO uint32_t  PA_CLK     :  1;               /*!< Enables clock for GPIO port 0                                         */
      __IO uint32_t  DMA_CLK    :  1;               /*!< Enables clock for DMA                                                 */
      __IO uint32_t  PB_CLK     :  1;               /*!< Enables clock for GPIO port 1                                         */
      __IO uint32_t  PC_CLK     :  1;               /*!< Enables clock for GPIO port 1                                         */
      __IO uint32_t  RTC_CLK    :  1;               /*!< Enables gating clock for RTC                                          */
    } SYSAHBCLKCTRL_b;                              /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED3[23];
  
  union {
    __IO uint32_t  CLKOUTCLKSEL;                    /*!< Clockout clock source select register                                 */
    
    struct {
      __IO uint32_t  SEL        :  3;               /*!< CLKOUT clock source                                                   */
    } CLKOUTCLKSEL_b;                               /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CLKOUTUEN;                       /*!< Clockout clock source update enable register                          */
    
    struct {
      __IO uint32_t  ENA        :  3;               /*!< Enable CLKOUT clock source update                                     */
    } CLKOUTUEN_b;                                  /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CLKOUTDIV;                       /*!< Clockout clock divider register                                       */
    
    struct {
      __IO uint32_t  DIV        : 16;               /*!< Divider value                                                         */
    } CLKOUTDIV_b;                                  /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED4[5];
  
  union {
    __IO uint32_t  SLDOTRIM;                        /*!< Low power LDO trim register                                           */
    
    struct {
      __IO uint32_t  VTRIM      :  5;               /*!< Trim value                                                            */
    } SLDOTRIM_b;                                   /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  BODRESETSEL;                     /*!< BOD detect reset voltage selection register                           */
    
    struct {
      __IO uint32_t  VSEL       :  4;               /*!< Trim value                                                            */
    } BODRESETSEL_b;                                /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  BODINTSEL;                       /*!< BOD detect interrupt voltage selection register                       */
    
    struct {
      __IO uint32_t  VSEL       :  4;               /*!< Trim value                                                            */
    } BODINTSEL_b;                                  /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  WDTTRIM;                         /*!< WDT clock trim register                                               */
    
    struct {
      __IO uint32_t  TRIM       :  8;               /*!< Trim value                                                            */
    } WDTTRIM_b;                                    /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VREFTRIM;                        /*!< ADC internal VREF trim register                                       */
    
    struct {
      __IO uint32_t  VTRIM      :  8;               /*!< Voltage trim value                                                    */
    } VREFTRIM_b;                                   /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VDDHCTRL;                        /*!< VDDH divid selection register                                         */
    
    struct {
      __IO uint32_t  SEL        :  2;               /*!< Voltage selection value                                               */
    } VDDHCTRL_b;                                   /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VREFSEL;                         /*!< VREF selection register                                               */
    
    struct {
      __IO uint32_t  SEL        :  1;               /*!< VREF selection value                                                  */
    } VREFSEL_b;                                    /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  AD7SEL;                          /*!< AD7 input selection register                                          */
    
    struct {
      __IO uint32_t  SEL        :  1;               /*!< AD7 input selection value                                             */
    } AD7SEL_b;                                     /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  LDOWAKEUPCTRL;                   /*!< LDO wakeup control register                                           */
    
    struct {
      __IO uint32_t  LDOEN      :  1;               /*!< LDO wakeup control register                                           */
    } LDOWAKEUPCTRL_b;                              /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  RSTSTATCLR;                      /*!< MCU reset state clear register                                        */
    
    struct {
      __IO uint32_t  POR        :  1;               /*!< Clear POR reset flag                                                  */
      __IO uint32_t  BOD        :  1;               /*!< Clear BOD reset flag                                                  */
      __IO uint32_t  NRST       :  1;               /*!< Clear NRST reset flag                                                 */
      __IO uint32_t  WDT        :  1;               /*!< Clear WDT reset flag                                                  */
      __IO uint32_t  SYSRST     :  1;               /*!< Clear SYSRST reset flag                                               */
    } RSTSTATCLR_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  RSTSTAT;                         /*!< MCU reset state register                                              */
    
    struct {
      __I  uint32_t  POR        :  1;               /*!< POR reset flag                                                        */
      __I  uint32_t  BOD        :  1;               /*!< BOD reset flag                                                        */
      __I  uint32_t  NRST       :  1;               /*!< NRST reset flag                                                       */
      __I  uint32_t  WDT        :  1;               /*!< WDT reset flag                                                        */
      __I  uint32_t  SYSRST     :  1;               /*!< SYSRST reset flag                                                     */
    } RSTSTAT_b;                                    /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED5[9];
  
  union {
    __IO uint32_t  BODCTRL;                         /*!< BOD power down control register                                       */
    
    struct {
      __IO uint32_t  BODEN      :  1;               /*!< BOD detect enable                                                     */
      __IO uint32_t  BODENTERINTEN:  1;             /*!< BOD enter interrupt enable                                            */
      __IO uint32_t  BODEXITINTEN:  1;              /*!< BOD exit interrupt enable                                             */
           uint32_t             :  1;
      __IO uint32_t  BODRSTEN   :  1;               /*!< BOD reset enable                                                      */
      __IO uint32_t  BODRAWSTATE:  1;               /*!< BOD raw state                                                         */
      __IO uint32_t  BODENTERSTATUS:  1;            /*!< BOD enter interrupt status                                            */
      __IO uint32_t  BODEXITSTATUS:  1;             /*!< BOD exit interrupt status                                             */
    } BODCTRL_b;                                    /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  GRECORDER;                       /*!< General purpose data register                                         */
    
    struct {
      __IO uint32_t  DATA       : 16;               /*!< Data with POR reset only                                              */
    } GRECORDER_b;                                  /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED6[7];
  
  union {
    __IO uint32_t  INTNMI;                          /*!< NMI interrupt source configuration control                            */
    
    struct {
      __IO uint32_t  NMISRC     :  6;               /*!< NMI interrupts source select                                          */
    } INTNMI_b;                                     /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED7[48];
  
  union {
    __IO uint32_t  PDRUNCFG;                        /*!< Power-down configuration register                                     */
    
    struct {
      __IO uint32_t  FLASH_PD   :  1;               /*!< Flash power-down                                                      */
      __IO uint32_t  IRC_PD     :  1;               /*!< IRC oscillator power-down                                             */
      __IO uint32_t  WDTOSC_PD  :  1;               /*!< WDT oscillator power-down                                             */
      __IO uint32_t  ADC_PD     :  1;               /*!< ADC power-down                                                        */
      __IO uint32_t  CMP0_PD    :  1;               /*!< CMP0 power-down                                                       */
      __IO uint32_t  CMP1_PD    :  1;               /*!< CMP1 power-down                                                       */
      __IO uint32_t  VREF_PD    :  1;               /*!< ADC VREF power-down                                                   */
      __IO uint32_t  VDDDECT_PD :  1;               /*!< VDD dectect input power-down                                          */
      __IO uint32_t  OSC32_PD   :  1;               /*!< Ext 32K OSC power-down                                                */
      __IO uint32_t  SLDO_PD    :  1;               /*!< Low power LDO power-down                                              */
      __IO uint32_t  BOD_PD     :  1;               /*!< BOD power-down                                                        */
    } PDRUNCFG_b;                                   /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED8;
  
  union {
    __IO uint32_t  ADCCLKDIV;                       /*!< ADC clock divider register                                            */
    
    struct {
      __IO uint32_t  DIV        :  8;               /*!< Divider value                                                         */
    } ADCCLKDIV_b;                                  /*!< BitSize                                                               */
  };
} SYSCON_Type;


/* ================================================================================ */
/* ================                      IOCON                     ================ */
/* ================================================================================ */


/**
  * @brief I/O configuration block (IOCON)
  */

typedef struct {                                    /*!< IOCON Structure                                                       */
  
  union {
    __IO uint32_t  PA0;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA0_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA1;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA1_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA2;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA2_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA3;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA3_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA4;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA4_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA5;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA5_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA6;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA6_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA7;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA7_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA8;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA8_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA9;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA9_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA10;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA10_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA11;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA11_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA12;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA12_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA13;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA13_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA14;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA14_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PA15;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PA15_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB0;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB0_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB1;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB1_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB2;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB2_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB3;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB3_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB4;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB4_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB5;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB5_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB6;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB6_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB7;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB7_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB8;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB8_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB9;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB9_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB10;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB10_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB11;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB11_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB12;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB12_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB13;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB13_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB14;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB14_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PB15;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PB15_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC0;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC0_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC1;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC1_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC2;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC2_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC3;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC3_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC4;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC4_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC5;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC5_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC6;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC6_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC7;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC7_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC8;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC8_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC9;                             /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC9_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC10;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC10_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC11;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC11_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC12;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC12_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC13;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC13_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC14;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC14_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC15;                            /*!< Pin config register                                                   */
    
    struct {
      __IO uint32_t  FUNC       :  3;               /*!< Selects pin function                                                  */
      __IO uint32_t  PDE        :  1;               /*!< Pull-down mode                                                        */
      __IO uint32_t  PUE        :  1;               /*!< Pull-up mode                                                          */
      __IO uint32_t  CSE        :  1;               /*!< Schmitt trigger enable                                                */
      __IO uint32_t  INV        :  1;               /*!< Invert input                                                          */
      __IO uint32_t  SRM        :  1;               /*!< Slew rate mode                                                        */
      __IO uint32_t  ADM        :  1;               /*!< Analog mode                                                           */
      __IO uint32_t  DRV        :  1;               /*!< Drive current mode (Normal-drive pin)                                 */
      __IO uint32_t  OD         :  1;               /*!< Open-drain mode                                                       */
           uint32_t             :  1;
      __IO uint32_t  INE        :  1;               /*!< Input Enable                                                          */
    } PC15_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PINREMAP;                        /*!< Pin remap Register                                                    */
    
    struct {
      __IO uint32_t  PC7_REMAP  :  1;               /*!< PC7 remap bit                                                         */
      __IO uint32_t  PC9_REMAP  :  1;               /*!< PC9 remap bit                                                         */
    } PINREMAP_b;                                   /*!< BitSize                                                               */
  };
} IOCON_Type;


/* ================================================================================ */
/* ================                      UART0                     ================ */
/* ================================================================================ */


/**
  * @brief Universal asynchronous receiver/transmitter (UART0)
  */

typedef struct {                                    /*!< UART0 Structure                                                       */
  __I  uint32_t  RBR;                               /*!< Receiver Buffer Register                                              */
  __O  uint32_t  THR;                               /*!< Transmit Holding Register                                             */
  
  union {
    __IO uint32_t  DLR;                             /*!< Divisor Latch Register                                                */
    
    struct {
      __IO uint32_t  DLR        : 16;               /*!< Baud rate dividor                                                     */
    } DLR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  IER;                             /*!< Interrupt Enable Register                                             */
    
    struct {
      __IO uint32_t  RBRIE      :  1;               /*!< RX Buffer Register Interrupt Enable.                                  */
      __IO uint32_t  THREIE     :  1;               /*!< TX Holding Register Empty Interrupt Enable                            */
      __IO uint32_t  RLSIE      :  1;               /*!< RX Line Status Interrupt Enable                                       */
      __IO uint32_t  MDSIE      :  1;               /*!< Modem Status Interrupt Enable.                                        */
           uint32_t             :  1;
      __IO uint32_t  XOFIE      :  1;               /*!< XOFF Interrupt Enable.                                                */
      __IO uint32_t  RTSIE      :  1;               /*!< RTS Interrupt Enable                                                  */
      __IO uint32_t  CTSIE      :  1;               /*!< CTS Interrupt Enable                                                  */
    } IER_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  IIR;                             /*!< Interrupt Identification Register                                     */
    
    struct {
      __I  uint32_t  INTSTATUS  :  1;               /*!< nterrupt status.                                                      */
      __I  uint32_t  INTID      :  3;               /*!< Interrupt identification                                              */
      __I  uint32_t  INTSFC     :  1;               /*!< Software Flow Control                                                 */
      __I  uint32_t  INTHFC     :  1;               /*!< Hardware Flow Control                                                 */
    } IIR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  FCR;                             /*!< FIFO Control Register                                                 */
    
    struct {
      __IO uint32_t  FIFOEN     :  1;               /*!< FIFO Enable                                                           */
      __IO uint32_t  RXFIFORST  :  1;               /*!< RX FIFO Reset                                                         */
      __IO uint32_t  TXFIFORST  :  1;               /*!< TX FIFO Reset                                                         */
           uint32_t             :  1;
      __IO uint32_t  TXTL       :  2;               /*!< TX Trigger Level                                                      */
      __IO uint32_t  RXTL       :  2;               /*!< RX Trigger Level.                                                     */
    } FCR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  LCR;                             /*!< Line Control Register                                                 */
    
    struct {
      __IO uint32_t  WLS        :  2;               /*!< Word Length Select                                                    */
      __IO uint32_t  SBS        :  1;               /*!< Stop Bit Select                                                       */
      __IO uint32_t  PEN        :  1;               /*!< Parity Enable                                                         */
      __IO uint32_t  PSEL       :  2;               /*!< Parity Select                                                         */
      __IO uint32_t  BCON       :  1;               /*!< Break Control                                                         */
      __IO uint32_t  BIT9EN     :  1;               /*!< Enable transimit 9-bit data at parity position, PEN must be
                                                         enable at same time                                                   */
    } LCR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MCR;                             /*!< Modem control register                                                */
    
    struct {
           uint32_t             :  1;
      __IO uint32_t  RTS        :  1;               /*!< Source for modem output pin RTS                                       */
           uint32_t             :  2;
      __IO uint32_t  MLBM       :  1;               /*!< Modem Loop back mode                                                  */
           uint32_t             :  1;
      __IO uint32_t  IREN       :  1;               /*!< IrDA mode enables                                                     */
      __IO uint32_t  XOFFS      :  1;               /*!< XOFF Status                                                           */
    } MCR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  LSR;                             /*!< Line Status Register                                                  */
    
    struct {
      __I  uint32_t  RDR        :  1;               /*!< Receiver Data Ready:                                                  */
      __I  uint32_t  OE         :  1;               /*!< Overrun Error.                                                        */
      __I  uint32_t  PE         :  1;               /*!< Parity Error                                                          */
      __I  uint32_t  FE         :  1;               /*!< Framing Error                                                         */
      __I  uint32_t  BI         :  1;               /*!< Break Interrupt                                                       */
      __I  uint32_t  THRE       :  1;               /*!< Transmitter Holding Register Empty.                                   */
      __I  uint32_t  TEMT       :  1;               /*!< Transmitter Empty                                                     */
      __I  uint32_t  RXFE       :  1;               /*!< Error in RX FIFO                                                      */
    } LSR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  MSR;                             /*!< Modem status register                                                 */
    
    struct {
      __I  uint32_t  DCTS       :  1;               /*!< Delta CTS                                                             */
           uint32_t             :  3;
      __I  uint32_t  CTS        :  1;               /*!< Clear To Send State.                                                  */
    } MSR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  SCR;                             /*!< Scratch Pad Register                                                  */
    
    struct {
      __IO uint32_t  PAD        : 31;               /*!< Scratch Pad Register                                                  */
    } SCR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  EFR;                             /*!< Enhanced FeatUARTes Register                                          */
    
    struct {
      __IO uint32_t  RXSWFC     :  2;               /*!< RX Software Flow Control                                              */
      __IO uint32_t  TXSWFC     :  2;               /*!< TX Software Flow Control                                              */
      __IO uint32_t  MEEN       :  1;               /*!< M16x50 Enhancements Enables                                           */
      __IO uint32_t  AUTORTS    :  1;               /*!< Enables hardware reception flow control                               */
      __IO uint32_t  AUTOCTS    :  1;               /*!< Enables hardware transmission flow control                            */
    } EFR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  XON1;                            /*!< flow control Register                                                 */
    
    struct {
      __IO uint32_t  HXON       :  8;               /*!< hold the XON characters used in software control of transmission
                                                         and reception                                                         */
    } XON1_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  XON2;                            /*!< flow control Register Register                                        */
    
    struct {
      __IO uint32_t  HXON       :  8;               /*!< hold the XON characters used in software control of transmission
                                                         and reception                                                         */
    } XON2_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  XOFF1;                           /*!< flow control RegisterRegister                                         */
    
    struct {
      __IO uint32_t  HXOFF      :  8;               /*!< hold the XOFF characters used in software control of transmission
                                                         and reception                                                         */
    } XOFF1_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  XOFF2;                           /*!< flow control Register Register                                        */
    
    struct {
      __IO uint32_t  HXOFF      :  8;               /*!< hold the XOFF characters used in software control of transmission
                                                         and reception                                                         */
    } XOFF2_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  FRAC;                            /*!< Dividor Fraction                                                      */
    
    struct {
      __IO uint32_t  FRACVAL    :  4;               /*!< Dividor Fraction                                                      */
    } FRAC_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DMAEN;                           /*!< DMA Enable                                                            */
    
    struct {
      __IO uint32_t  RXDMAE     :  1;               /*!< UART RX DMA enable                                                    */
      __IO uint32_t  TXDMAE     :  1;               /*!< UART TX DMA enable                                                    */
    } DMAEN_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  TXSTAT;                          /*!< UART transimit state                                                  */
    
    struct {
      __I  uint32_t  BSY        :  4;               /*!< UART transimit state                                                  */
    } TXSTAT_b;                                     /*!< BitSize                                                               */
  };
} UART0_Type;


/* ================================================================================ */
/* ================                      SPI0                      ================ */
/* ================================================================================ */


/**
  * @brief Serial peripheral interface (SPI0)
  */

typedef struct {                                    /*!< SPI0 Structure                                                        */
  
  union {
    __IO uint32_t  CON;                             /*!< SSP Control Register.                                                 */
    
    struct {
      __IO uint32_t  DSS        :  4;               /*!< Data Size Select                                                      */
      __IO uint32_t  FRF        :  2;               /*!< Frame Format                                                          */
      __IO uint32_t  CPO        :  1;               /*!< Clock Out Polarity                                                    */
      __IO uint32_t  CPH        :  1;               /*!< Clock Out Phase                                                       */
      __IO uint32_t  SOD        :  1;               /*!< Slave Output Disable.                                                 */
      __IO uint32_t  MS         :  1;               /*!< Master/Slave Mode.                                                    */
      __IO uint32_t  SSPEN      :  1;               /*!< SSP Enable.                                                           */
      __IO uint32_t  LBM        :  1;               /*!< Loop Back Mode.                                                       */
      __IO uint32_t  LSBFIRST   :  1;               /*!< Frame format                                                          */
    } CON_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  STAT;                            /*!< SSP Status Register.                                                  */
    
    struct {
      __I  uint32_t  TFE        :  1;               /*!< Transmit FIFO Empty                                                   */
      __I  uint32_t  TNF        :  1;               /*!< Transmit FIFO Not Full.                                               */
      __I  uint32_t  RNE        :  1;               /*!< Receive FIFO Not Empty.                                               */
      __I  uint32_t  RFF        :  1;               /*!< Receive FIFO Full.                                                    */
      __I  uint32_t  BSY        :  1;               /*!< Busy                                                                  */
    } STAT_b;                                       /*!< BitSize                                                               */
  };
  __IO uint32_t  DAT;                               /*!< SSP Data Register                                                     */
  
  union {
    __IO uint32_t  CLK;                             /*!< SSP Clock Control Register.                                           */
    
    struct {
      __IO uint32_t  N          :  8;               /*!< N                                                                     */
      __IO uint32_t  M          :  8;               /*!< M                                                                     */
    } CLK_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  IMSC;                            /*!< SSP Interrupt Mask Set and Clear Register.                            */
    
    struct {
      __IO uint32_t  RORIM      :  1;               /*!< Receive Overrun Interrupt Mask.                                       */
      __IO uint32_t  RTIM       :  1;               /*!< Receive Timeout Interrupt Mask.                                       */
      __IO uint32_t  RXIM       :  1;               /*!< Receive FIFO Interrupt Mask.                                          */
      __IO uint32_t  TXIM       :  1;               /*!< Transmit FIFO Interrupt Mask.                                         */
    } IMSC_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  RIS;                             /*!< SSP Raw Interrupt Status Register.                                    */
    
    struct {
      __I  uint32_t  RORRIS     :  1;               /*!< This bit is 1 if another frame was completely received while
                                                         the Rx FIFO was full.                                                 */
      __I  uint32_t  RTRIS      :  1;               /*!< This bit is 1 if the Rx FIFO is not empty, and has not been
                                                         read for a time-out period.                                           */
      __I  uint32_t  RXRIS      :  1;               /*!< This bit is 1 if the Rx FIFO is at least half full.                   */
      __I  uint32_t  TXRIS      :  1;               /*!< This bit is 1 if the Tx FIFO is at least half empty.                  */
    } RIS_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  MIS;                             /*!< SSP Masked Interrupt Status Register.                                 */
    
    struct {
      __I  uint32_t  RORMIS     :  1;               /*!< This bit is 1 if another frame was completely received while
                                                         the Rx FIFO was full, and this interrupt is enabled.                  */
      __I  uint32_t  RTMIS      :  1;               /*!< This bit is 1 if the Rx FIFO is not empty, has not been read
                                                         for a time-out period,                                                */
      __I  uint32_t  RXMIS      :  1;               /*!< This bit is 1 if the Rx FIFO is at least half full, and this
                                                         interrupt is enabled.                                                 */
      __I  uint32_t  TXMIS      :  1;               /*!< This bit is 1 if the Tx FIFO is at least half empty, and this
                                                         interrupt is enabled.                                                 */
    } MIS_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  ICLR;                            /*!< SSP Interrupt Clear Register.                                         */
    
    struct {
      __O  uint32_t  RORIC      :  1;               /*!< Writing a 1 to this bit clears the frame was received when Rx
                                                         FIFO was full interrupt.                                              */
      __O  uint32_t  RTIC       :  1;               /*!< Writing a 1 to this bit clears the Rx FIFO was not empty and
                                                         has not been read for a timeout period interrupt.                     */
    } ICLR_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DMACR;                           /*!< DMA control register                                                  */
    
    struct {
      __IO uint32_t  RXDMAE     :  1;               /*!< Receive DMA Enable                                                    */
      __IO uint32_t  TXDMAE     :  1;               /*!< Transmit DMA Enable                                                   */
    } DMACR_b;                                      /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED;
  
  union {
    __IO uint32_t  CSCR;                            /*!< Software Control SSP CS.                                              */
    
    struct {
      __IO uint32_t  SELCS      :  2;               /*!< SS0~SS3 line active select                                            */
      __IO uint32_t  SWSEL      :  1;               /*!< software controlled by SWCS bit                                       */
      __IO uint32_t  SWCS       :  1;               /*!< Software Chip-Select.                                                 */
      __IO uint32_t  SPHDONTCARE:  1;               /*!< As SSP slave.                                                         */
    } CSCR_b;                                       /*!< BitSize                                                               */
  };
} SPI0_Type;


/* ================================================================================ */
/* ================                      I2C0                      ================ */
/* ================================================================================ */


/**
  * @brief two wires serial communication interface (I2C0)
  */

typedef struct {                                    /*!< I2C0 Structure                                                        */
  
  union {
    __IO uint32_t  CONSET;                          /*!< I2C control set bit register                                          */
    
    struct {
      __IO uint32_t  ADRF       :  1;               /*!< I2C Slave Address FLAG                                                */
      __IO uint32_t  XADRF      :  1;               /*!< 2C Extended Slave Address FLAG                                        */
      __IO uint32_t  AA         :  1;               /*!< Assert acknowledge flag                                               */
      __IO uint32_t  SI         :  1;               /*!< I2C interrupt flag                                                    */
      __IO uint32_t  STO        :  1;               /*!< STOP flag                                                             */
      __IO uint32_t  STA        :  1;               /*!< START flag                                                            */
      __IO uint32_t  I2CEN      :  1;               /*!< I2C interface enable                                                  */
      __IO uint32_t  I2CIE      :  1;               /*!< Interrupt Enable                                                      */
      __IO uint32_t  GCF        :  1;               /*!< I2C General Call FLAG                                                 */
    } CONSET_b;                                     /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  CONCLR;                          /*!< I2C control clear bit register                                        */
    
    struct {
           uint32_t             :  2;
      __O  uint32_t  AAC        :  1;               /*!< Assert acknowledge Clear                                              */
      __O  uint32_t  SIC        :  1;               /*!< I2C interrupt Clear                                                   */
           uint32_t             :  1;
      __O  uint32_t  STAC       :  1;               /*!< START flag Clear                                                      */
      __O  uint32_t  I2CENC     :  1;               /*!< I2C interface Disable                                                 */
      __O  uint32_t  I2CIEC     :  1;               /*!< I2C interrupt Disable                                                 */
    } CONCLR_b;                                     /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  STAT;                            /*!< I2C state register                                                    */
    
    struct {
           uint32_t             :  3;
      __I  uint32_t  STATUS     :  5;               /*!< These bits give the actual status information about the I2C
                                                         interface                                                             */
    } STAT_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DAT;                             /*!< I2C data register                                                     */
    
    struct {
      __IO uint32_t  DATA       :  8;               /*!< This register holds data values that have been received or are
                                                         to be transmitted                                                     */
    } DAT_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CLK;                             /*!< I2C clock control register                                            */
    
    struct {
      __IO uint32_t  N          :  4;               /*!< N                                                                     */
      __IO uint32_t  M          :  3;               /*!< M                                                                     */
    } CLK_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ADR0;                            /*!< I2C Slave Address Register 0                                          */
    
    struct {
      __IO uint32_t  GC         :  1;               /*!< General Call enable bit                                               */
      __IO uint32_t  ADDRESS    :  7;               /*!< The I2C device address for slave mode                                 */
    } ADR0_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ADM0;                            /*!< I2C Slave Address Mask Register 0                                     */
    
    struct {
           uint32_t             :  1;
      __IO uint32_t  MASK       :  7;               /*!< Mask bits                                                             */
    } ADM0_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  XADR0;                           /*!< I2C Extended Slave Address Register 0                                 */
    
    struct {
           uint32_t             :  1;
      __IO uint32_t  ADDRESS    : 10;               /*!< The I2C device address for slave mode                                 */
    } XADR0_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  XADM0;                           /*!< I2C Extended Slave Address Mask Register 0                            */
    
    struct {
           uint32_t             :  1;
      __O  uint32_t  MASK       :  7;               /*!< Mask bits                                                             */
    } XADM0_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  RST;                             /*!< I2C Software Reset Register                                           */
    
    struct {
      __O  uint32_t  RST        :  8;               /*!< I2C software reset by writes 0x07                                     */
    } RST_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ADR1;                            /*!< I2C Slave Address Register 1                                          */
    
    struct {
      __IO uint32_t  GC         :  1;               /*!< General Call enable bit                                               */
      __IO uint32_t  ADDRESS    :  7;               /*!< The I2C device address for slave mode                                 */
    } ADR1_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ADM1;                            /*!< I2C Slave Address Mask Register 0                                     */
    
    struct {
           uint32_t             :  1;
      __IO uint32_t  MASK       :  7;               /*!< Mask bits                                                             */
    } ADM1_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ADR2;                            /*!< I2C slave address register2                                           */
    
    struct {
      __IO uint32_t  GC         :  1;               /*!< General Call enable bit                                               */
      __IO uint32_t  ADDRESS    :  7;               /*!< The I2C device address for slave mode                                 */
    } ADR2_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ADM2;                            /*!< I2C address mask register2                                            */
    
    struct {
           uint32_t             :  1;
      __IO uint32_t  MASK       :  7;               /*!< Mask bits                                                             */
    } ADM2_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ADR3;                            /*!< I2C slave address register3                                           */
    
    struct {
      __IO uint32_t  GC         :  1;               /*!< General Call enable bit                                               */
      __IO uint32_t  ADDRESS    :  7;               /*!< The I2C device address for slave mode                                 */
    } ADR3_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ADM3;                            /*!< I2C address mask register3                                            */
    
    struct {
           uint32_t             :  1;
      __IO uint32_t  MASK       :  7;               /*!< Mask bits                                                             */
    } ADM3_b;                                       /*!< BitSize                                                               */
  };
} I2C0_Type;


/* ================================================================================ */
/* ================                       RTC                      ================ */
/* ================================================================================ */


/**
  * @brief 24 bits RTC Counter (RTC)
  */

typedef struct {                                    /*!< RTC Structure                                                         */
  
  union {
    __IO uint32_t  CTRL;                            /*!< RTC control register                                                  */
    
    struct {
      __IO uint32_t  RTCEN      :  1;               /*!< RTC enable                                                            */
      __IO uint32_t  INTEN      :  1;               /*!< RTC match interrupt                                                   */
    } CTRL_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MR;                              /*!< RTC match register                                                    */
    
    struct {
      __IO uint32_t  MAT        : 24;               /*!< MAT value                                                             */
    } MR_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  TC;                              /*!< RTC counter register                                                  */
    
    struct {
      __IO uint32_t  TC         : 24;               /*!< RTC counter value                                                     */
    } TC_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  INTS;                            /*!< Interrupt status register                                             */
    
    struct {
      __IO uint32_t  INTS       :  1;               /*!< Interrupt status                                                      */
    } INTS_b;                                       /*!< BitSize                                                               */
  };
} RTC_Type;


/* ================================================================================ */
/* ================                      BTIM0                     ================ */
/* ================================================================================ */


/**
  * @brief 16 bits timer (BTIM0)
  */

typedef struct {                                    /*!< BTIM0 Structure                                                       */
  
  union {
    __IO uint32_t  IR;                              /*!< Interrupt register                                                    */
    
    struct {
      __IO uint32_t  MR0INT     :  1;               /*!< interrupt flag for match channel 0                                    */
      __IO uint32_t  MR1INT     :  1;               /*!< interrupt flag for match channel 1                                    */
    } IR_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  TCR;                             /*!< Timer control register                                                */
    
    struct {
      __IO uint32_t  CEN        :  1;               /*!< Counter enable                                                        */
      __IO uint32_t  CRST       :  1;               /*!< Counter reset                                                         */
      __IO uint32_t  SWAPEN     :  1;               /*!< Swap MAT0 and MAT0N output                                            */
      __IO uint32_t  MAT0INV    :  1;               /*!< Inverse MAT0 output                                                   */
      __IO uint32_t  MAT1INV    :  1;               /*!< Inverse MAT0N output                                                  */
      __IO uint32_t  MOD        :  1;               /*!< Timer mode                                                            */
    } TCR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  TC;                              /*!< Timer counter register                                                */
    
    struct {
      __IO uint32_t  TC         : 16;               /*!< Timer counter value                                                   */
    } TC_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PR;                              /*!< Prescale register                                                     */
    
    struct {
      __IO uint32_t  PRVAL      : 16;               /*!< Prescale value                                                        */
    } PR_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC;                              /*!< Prescale Counter register                                             */
    
    struct {
      __IO uint32_t  PCVAL      : 16;               /*!< Prescale counter value                                                */
    } PC_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MCR;                             /*!< Match Control Register                                                */
    
    struct {
      __IO uint32_t  MR0I       :  1;               /*!< Interrupt on MR0                                                      */
      __IO uint32_t  MR1I       :  1;               /*!< Interrupt on MR1                                                      */
      __IO uint32_t  MR1R       :  1;               /*!< Reset on MR1                                                          */
      __IO uint32_t  MR1S       :  1;               /*!< Stop on MR1                                                           */
    } MCR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MR0;                             /*!< Match register0                                                       */
    
    struct {
      __IO uint32_t  MATCH      : 16;               /*!< Timer counter match value                                             */
    } MR0_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MR1;                             /*!< Match register1                                                       */
    
    struct {
      __IO uint32_t  MATCH      : 16;               /*!< Timer counter match value                                             */
    } MR1_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DT0;                             /*!< Deat time register 0                                                  */
    
    struct {
      __IO uint32_t  DEADTIME   : 16;               /*!< Dead time value                                                       */
    } DT0_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DT1;                             /*!< Deat time register 1                                                  */
    
    struct {
      __IO uint32_t  DEADTIME   : 16;               /*!< Dead time value                                                       */
    } DT1_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DTEN;                            /*!< Deat time enable                                                      */
    
    struct {
      __IO uint32_t  DTEN       :  1;               /*!< Dead time enable                                                      */
    } DTEN_b;                                       /*!< BitSize                                                               */
  };
} BTIM0_Type;


/* ================================================================================ */
/* ================                      CTIM0                     ================ */
/* ================================================================================ */


/**
  * @brief 16 bits timer (CTIM0)
  */

typedef struct {                                    /*!< CTIM0 Structure                                                       */
  
  union {
    __IO uint32_t  IR;                              /*!< Interrupt register                                                    */
    
    struct {
      __IO uint32_t  MR0INT     :  1;               /*!< Interrupt flag for match channel 0                                    */
      __IO uint32_t  MR1INT     :  1;               /*!< Interrupt flag for match channel 1                                    */
      __IO uint32_t  MR2INT     :  1;               /*!< Interrupt flag for match channel 2                                    */
      __IO uint32_t  MR3INT     :  1;               /*!< Interrupt flag for match channel 3                                    */
      __IO uint32_t  CR0INT     :  1;               /*!< Interrupt flag for capture channel 0 event                            */
      __IO uint32_t  CR1INT     :  1;               /*!< Interrupt flag for capture channel 1 event                            */
      __IO uint32_t  CR2INT     :  1;               /*!< Interrupt flag for capture channel 2 event                            */
      __IO uint32_t  CR3INT     :  1;               /*!< Interrupt flag for capture channel 3 event                            */
    } IR_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  TCR;                             /*!< Timer control register                                                */
    
    struct {
      __IO uint32_t  CEN        :  1;               /*!< Counter enable                                                        */
      __IO uint32_t  CRST       :  1;               /*!< Counter reset                                                         */
           uint32_t             :  2;
      __IO uint32_t  RELAOD     :  1;               /*!< Enable timer relaod                                                   */
      __IO uint32_t  MAT0INV    :  1;               /*!< Reverse MAT0 output                                                   */
      __IO uint32_t  MAT1INV    :  1;               /*!< Reverse MAT1 output                                                   */
      __IO uint32_t  MAT2INV    :  1;               /*!< Reverse MAT2 output                                                   */
      __IO uint32_t  MAT3INV    :  1;               /*!< Reverse MAT3 output                                                   */
      __IO uint32_t  DMAEN_MAT0 :  1;               /*!< Enable MAT0 DMA                                                       */
      __IO uint32_t  DMAEN_MAT1 :  1;               /*!< Enable MAT1 DMA                                                       */
    } TCR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  TC;                              /*!< Timer counter register                                                */
    
    struct {
      __IO uint32_t  TC         : 16;               /*!< Timer counter value                                                   */
    } TC_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PR;                              /*!< Prescale register                                                     */
    
    struct {
      __IO uint32_t  PCVAL      : 16;               /*!< Prescale value                                                        */
    } PR_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PC;                              /*!< Prescale Counter register                                             */
    
    struct {
      __IO uint32_t  PC         : 16;               /*!< Prescale counter value                                                */
    } PC_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MCR;                             /*!< Match Control Register                                                */
    
    struct {
      __IO uint32_t  MR0I       :  1;               /*!< Interrupt on MR0                                                      */
      __IO uint32_t  MR0R       :  1;               /*!< Reset on MR0                                                          */
      __IO uint32_t  MR0S       :  1;               /*!< Stop on MR0                                                           */
      __IO uint32_t  MR1I       :  1;               /*!< Interrupt on MR1                                                      */
      __IO uint32_t  MR1R       :  1;               /*!< Reset on MR1                                                          */
      __IO uint32_t  MR1S       :  1;               /*!< Stop on MR1                                                           */
      __IO uint32_t  MR2I       :  1;               /*!< Interrupt on MR2                                                      */
      __IO uint32_t  MR2R       :  1;               /*!< Reset on MR2                                                          */
      __IO uint32_t  MR2S       :  1;               /*!< Stop on MR2                                                           */
      __IO uint32_t  MR3I       :  1;               /*!< Interrupt on MR3                                                      */
      __IO uint32_t  MR3R       :  1;               /*!< Reset on MR3                                                          */
      __IO uint32_t  MR3S       :  1;               /*!< Stop on MR3                                                           */
    } MCR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MR0;                             /*!< Match register0                                                       */
    
    struct {
      __IO uint32_t  MATCH      : 16;               /*!< Timer counter match value                                             */
    } MR0_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MR1;                             /*!< Match register1                                                       */
    
    struct {
      __IO uint32_t  MATCH      : 16;               /*!< Timer counter match value                                             */
    } MR1_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MR2;                             /*!< Match register2                                                       */
    
    struct {
      __IO uint32_t  MATCH      : 16;               /*!< Timer counter match value                                             */
    } MR2_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  MR3;                             /*!< Match register3                                                       */
    
    struct {
      __IO uint32_t  MATCH      : 16;               /*!< Timer counter match value                                             */
    } MR3_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CCR;                             /*!< Capture Control Register                                              */
    
    struct {
      __IO uint32_t  CAP0RE     :  1;               /*!< Capture on CT16Bn_CAP0 rising edge                                    */
      __IO uint32_t  CAP0FE     :  1;               /*!< Capture on CT16Bn_CAP0 falling edge                                   */
      __IO uint32_t  CAP0I      :  1;               /*!< Interrupt on CT16Bn_CAP0 event                                        */
      __IO uint32_t  CAP1RE     :  1;               /*!< Capture on CT16Bn_CAP1 rising edge                                    */
      __IO uint32_t  CAP1FE     :  1;               /*!< Capture on CT16Bn_CAP1 falling edge                                   */
      __IO uint32_t  CAP1I      :  1;               /*!< Interrupt on CT16Bn_CAP1 event                                        */
      __IO uint32_t  CAP2RE     :  1;               /*!< Capture on comparator n level output_rising edge                      */
      __IO uint32_t  CAP2FE     :  1;               /*!< Capture on comparator n level output_falling edge                     */
      __IO uint32_t  CAP2I      :  1;               /*!< Interrupt on comparator n level output event                          */
      __IO uint32_t  CAP3RE     :  1;               /*!< Capture on comparator n edge output_rising edge                       */
      __IO uint32_t  CAP3FE     :  1;               /*!< Capture on comparator n edge output_falling edge                      */
      __IO uint32_t  CAP3I      :  1;               /*!< Interrupt on comparator n edge output event                           */
    } CCR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  CR0;                             /*!< Capture register0                                                     */
    
    struct {
      __I  uint32_t  CAP        : 16;               /*!< Timer counter capture value                                           */
    } CR0_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  CR1;                             /*!< Capture register1                                                     */
    
    struct {
      __I  uint32_t  CAP        : 16;               /*!< Timer counter capture value                                           */
    } CR1_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  CR2;                             /*!< Capture register2                                                     */
    
    struct {
      __I  uint32_t  CAP        : 16;               /*!< Timer counter capture value                                           */
    } CR2_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  CR3;                             /*!< Capture register3                                                     */
    
    struct {
      __I  uint32_t  CAP        : 16;               /*!< Timer counter capture value                                           */
    } CR3_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  EMR;                             /*!< External match register                                               */
    
    struct {
      __IO uint32_t  EM0        :  1;               /*!< External match 0                                                      */
      __IO uint32_t  EM1        :  1;               /*!< External match 1                                                      */
      __IO uint32_t  EM2        :  1;               /*!< External match 2                                                      */
      __IO uint32_t  EM3        :  1;               /*!< External match 3                                                      */
      __IO uint32_t  EMC0       :  2;               /*!< External match Control 0                                              */
      __IO uint32_t  EMC1       :  2;               /*!< External match Control 1                                              */
      __IO uint32_t  EMC2       :  2;               /*!< External match Control 2                                              */
      __IO uint32_t  EMC3       :  2;               /*!< External match Control 3                                              */
    } EMR_b;                                        /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED[12];
  
  union {
    __IO uint32_t  CTCR;                            /*!< Counter control register                                              */
    
    struct {
      __IO uint32_t  CTM        :  3;               /*!< Counter/Timer Mode                                                    */
      __IO uint32_t  ENCC       :  1;               /*!< Enable SELCC slection to clear timer and prescaler                    */
      __IO uint32_t  SELCC      :  4;               /*!< Selection to clear timer and prescaler                                */
      __IO uint32_t  PRISEL     :  4;               /*!< Primary clock source select                                           */
      __IO uint32_t  SECSEL     :  4;               /*!< Secondary clock source select                                         */
      __IO uint32_t  IPS        :  1;               /*!< Secondary source input polarity select                                */
    } CTCR_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PWMC;                            /*!< PWM Control Register                                                  */
    
    struct {
      __IO uint32_t  PWMEN0     :  1;               /*!< PWM mode enable for channel0                                          */
      __IO uint32_t  PWMEN1     :  1;               /*!< PWM mode enable for channel1                                          */
      __IO uint32_t  PWMEN2     :  1;               /*!< PWM mode enable for channel2                                          */
    } PWMC_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CAPFILTER0;                      /*!< Capture channel 0 filter Register                                     */
    
    struct {
      __IO uint32_t  FILTER     : 16;               /*!< Capture filter                                                        */
    } CAPFILTER0_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CAPFILTER1;                      /*!< Capture channel 1 filter Register                                     */
    
    struct {
      __IO uint32_t  FILTER     : 16;               /*!< Capture filter                                                        */
    } CAPFILTER1_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CAPFILTER2;                      /*!< Capture channel 2 filter Register                                     */
    
    struct {
      __IO uint32_t  FILTER     : 16;               /*!< Capture filter                                                        */
    } CAPFILTER2_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CAPFILTER3;                      /*!< Capture channel 3 filter Register                                     */
    
    struct {
      __IO uint32_t  FILTER     : 16;               /*!< Capture filter                                                        */
    } CAPFILTER3_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CAPFILTEREN;                     /*!< Capture filter enable Register                                        */
    
    struct {
      __IO uint32_t  FILTER0EN  :  1;               /*!< Capture filter 0 enable                                               */
      __IO uint32_t  FILTER1EN  :  1;               /*!< Capture filter 1 enable                                               */
      __IO uint32_t  FILTER2EN  :  1;               /*!< Capture filter 2 enable                                               */
      __IO uint32_t  FILTER3EN  :  1;               /*!< Capture filter 3 enable                                               */
    } CAPFILTEREN_b;                                /*!< BitSize                                                               */
  };
} CTIM0_Type;


/* ================================================================================ */
/* ================                       WDT                      ================ */
/* ================================================================================ */


/**
  * @brief Watch dog (WDT)
  */

typedef struct {                                    /*!< WDT Structure                                                         */
  
  union {
    __IO uint32_t  MOD;                             /*!< WDT mode register                                                     */
    
    struct {
      __IO uint32_t  WDEN       :  1;               /*!< Watchdog enable bit                                                   */
      __IO uint32_t  WDRESET    :  1;               /*!< Watchdog reset enable bit                                             */
      __IO uint32_t  WDTOF      :  1;               /*!< Watchdog time-out flag                                                */
      __IO uint32_t  WDINT      :  1;               /*!< To be filled                                                          */
      __IO uint32_t  WDPROTECT  :  1;               /*!< Watchdog update mode                                                  */
      __IO uint32_t  WDLOCKCLK  :  1;               /*!< Watchdog clock lock bit                                               */
      __IO uint32_t  WDLOCKDP   :  1;               /*!< Power-down disable bit                                                */
      __IO uint32_t  WDLOCKEN   :  1;               /*!< Watchdog enables and reset lockout bit                                */
    } MOD_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  TC;                              /*!< Watchdog timer constant register                                      */
    
    struct {
      __IO uint32_t  WDTC       : 24;               /*!< Watchdog time-out interval                                            */
    } TC_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  FEED;                            /*!< Watchdog feed sequence register                                       */
    
    struct {
      __O  uint32_t  WDFEED     :  8;               /*!< Feed value should be 0xAA followed by 0x55                            */
    } FEED_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  TV;                              /*!< Watchdog timer value register                                         */
    
    struct {
      __I  uint32_t  WDTV       : 24;               /*!< Counter timer value                                                   */
    } TV_b;                                         /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED;
  
  union {
    __IO uint32_t  WARNINT;                         /*!< Watchdog Warning Interrupt compares value                             */
    
    struct {
      __IO uint32_t  WARNINT    : 10;               /*!< Watchdog warning interrupt compare value                              */
    } WARNINT_b;                                    /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  WINDOW;                          /*!< Watchdog Window compares value                                        */
    
    struct {
      __IO uint32_t  WDWINDOW   : 24;               /*!< Watchdog window value                                                 */
    } WINDOW_b;                                     /*!< BitSize                                                               */
  };
} WDT_Type;


/* ================================================================================ */
/* ================                       ADC                      ================ */
/* ================================================================================ */


/**
  * @brief Analog-to-Digital Converter (ADC)
  */

typedef struct {                                    /*!< ADC Structure                                                         */
  
  union {
    __IO uint32_t  CR;                              /*!< ADC control register                                                  */
    
    struct {
      __IO uint32_t  AINS01     :  1;               /*!< Eanble ADC channel 0/1 as differential input                          */
      __IO uint32_t  AINS23     :  1;               /*!< Eanble ADC channel 2/3 as differential input                          */
      __IO uint32_t  AINS45     :  1;               /*!< Eanble ADC channel 4/5 as differential input                          */
      __IO uint32_t  AINS67     :  1;               /*!< Eanble ADC channel 6/7 as differential input                          */
      __IO uint32_t  ADCVREF    :  3;               /*!< ADC VREF Configeration                                                */
      __IO uint32_t  ADCSHT     :  2;               /*!< ADC sample hold time configeration                                    */
      __IO uint32_t  ADCCR      :  1;               /*!< ADC max comvertion clock configeration                                */
      __IO uint32_t  CONV_CAL   :  1;               /*!< Enable ADC calibration                                                */
      __IO uint32_t  RST_ALL    :  1;               /*!< Reset ADC                                                             */
      __IO uint32_t  RST_NCAL   :  1;               /*!< Reset ADC without calibration                                         */
      __IO uint32_t  TAMUX      :  4;               /*!< Channlel hold time after sample                                       */
      __IO uint32_t  BURST      :  1;               /*!< Burst mode control                                                    */
      __IO uint32_t  CONV_ERR_CLR:  1;              /*!< Convertion error clear                                                */
      __IO uint32_t  CAL_ERR_CLR:  1;               /*!< Calibration error clear                                               */
      __IO uint32_t  START      :  4;               /*!< Conversion starts control                                             */
      __IO uint32_t  EDGE       :  1;               /*!< Start Edge control                                                    */
      __IO uint32_t  LSEN       :  1;               /*!< ADC lever shift enable                                                */
      __IO uint32_t  VREFP_SEL  :  1;               /*!< Select internal ldo out as VREFP                                      */
      __IO uint32_t  DMAEN      :  1;               /*!< Enable DMA                                                            */
    } CR_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  INTEN;                           /*!< ADC Interrupt Enable Register                                         */
    
    struct {
      __IO uint32_t  INTEN_CHN  :  8;               /*!< These bits allow control over which A/D channels generate interrupts
                                                         for conversion completion.                                            */
      __IO uint32_t  INTEN_VMID :  1;               /*!< VMID conversion completion interrupt enable                           */
      __IO uint32_t  INTEN_VREFP:  1;               /*!< VREFP conversion completion interrupt enable                          */
      __IO uint32_t  INTEN_VREFN:  1;               /*!< VREFN conversion completion interrupt enable                          */
    } INTEN_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CHNEN;                           /*!< ADC convertion Enable Register                                        */
    
    struct {
      __IO uint32_t  CHN        :  8;               /*!< These bits allow control over which A/D channels to convert           */
           uint32_t             :  1;
      __IO uint32_t  VMID       :  1;               /*!< VMID conversion enable                                                */
      __IO uint32_t  VREFP      :  1;               /*!< VREFP conversion enable                                               */
      __IO uint32_t  VREFN      :  1;               /*!< VREFN conversion enable                                               */
    } CHNEN_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CALCR;                           /*!< ADC calibration control Register                                      */
    
    struct {
      __IO uint32_t  CAL_EN     :  1;               /*!< ADC calibration enable                                                */
      __IO uint32_t  EOCAL_CLR  :  1;               /*!< Clear completion flag for next calibration                            */
    } CALCR_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR0;                             /*!< A/D Channel 0 Data Register                                           */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR0_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR1;                             /*!< A/D Channel 1 Data Register                                           */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR1_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR2;                             /*!< A/D Channel 2 Data Register                                           */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR2_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR3;                             /*!< A/D Channel 3 Data Register                                           */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR3_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR4;                             /*!< A/D Channel 4 Data Register                                           */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR4_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR5;                             /*!< A/D Channel 5 Data Register                                           */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR5_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR6;                             /*!< A/D Channel 6 Data Register                                           */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR6_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR7;                             /*!< A/D Channel 7 Data Register                                           */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR7_b;                                        /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED;
  
  union {
    __IO uint32_t  DR9;                             /*!< VMID Data Register                                                    */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR9_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR10;                            /*!< VREFP Data Register                                                   */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR10_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DR11;                            /*!< VREFN Data Register                                                   */
    
    struct {
      __IO uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
           uint32_t             : 18;
      __IO uint32_t  OVERRUN    :  1;               /*!< Conversion results overwritten                                        */
      __IO uint32_t  DONE       :  1;               /*!< This bit is set to 1 when an A/D conversion completes                 */
    } DR11_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  SSCR;                            /*!< ADC spftware trigger Register                                         */
    
    struct {
      __IO uint32_t  ADCTRIG    :  1;               /*!< Software trigger bit                                                  */
    } SSCR_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  GDR;                             /*!< ADC Conversion Data Register                                          */
    
    struct {
      __I  uint32_t  RESULT     : 12;               /*!< Conversion results                                                    */
      __I  uint32_t  CHN        :  4;               /*!< ADC Channel                                                           */
    } GDR_b;                                        /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED1[2];
  
  union {
    __IO uint32_t  STAT;                            /*!< ADC Status Register                                                   */
    
    struct {
      __IO uint32_t  CAL_ERR    :  1;               /*!< Calibration error                                                     */
      __IO uint32_t  CONV_ERR   :  1;               /*!< ADC convertion error                                                  */
      __IO uint32_t  EOCAL      :  1;               /*!< End of calibration                                                    */
      __IO uint32_t  EOC_CONV   :  1;               /*!< End of convertion                                                     */
      __IO uint32_t  SAMP_CONV  :  1;               /*!< Sample                                                                */
      __IO uint32_t  BUSY       :  1;               /*!< ADC busy                                                              */
    } STAT_b;                                       /*!< BitSize                                                               */
  };
} ADC_Type;


/* ================================================================================ */
/* ================                       PMU                      ================ */
/* ================================================================================ */


/**
  * @brief Power management unit (PMU)
  */

typedef struct {                                    /*!< PMU Structure                                                         */
  
  union {
    __IO uint32_t  PCON;                            /*!< Power control register                                                */
    
    struct {
           uint32_t             :  1;
      __IO uint32_t  DPDEN      :  1;               /*!< Power-down mode enable                                                */
           uint32_t             :  6;
      __IO uint32_t  SLEEPFLAG  :  1;               /*!< Sleep mode flag                                                       */
           uint32_t             :  2;
      __IO uint32_t  DPDFLAG    :  1;               /*!< Power-down flag                                                       */
    } PCON_b;                                       /*!< BitSize                                                               */
  };
} PMU_Type;


/* ================================================================================ */
/* ================                       PWM                      ================ */
/* ================================================================================ */


/**
  * @brief Pulse-Width Modulation (PWM)
  */

typedef struct {                                    /*!< PWM Structure                                                         */
  
  union {
    __IO uint32_t  CTRL;                            /*!< Control Register                                                      */
    
    struct {
      __IO uint32_t  PWMEN      :  1;               /*!< PWM enable                                                            */
      __IO uint32_t  LDOK       :  1;               /*!< Load vaule bit                                                        */
      __IO uint32_t  PWMF       :  1;               /*!< PWM reload flag bit                                                   */
      __IO uint32_t  PWMRIE     :  1;               /*!< PWMF interrupt control bit                                            */
           uint32_t             :  3;
      __IO uint32_t  IPOL0      :  1;               /*!< Select the PWM value register for the PWM_0 and PWM_1 pins pair
                                                         in complementary mode                                                 */
      __IO uint32_t  IPOL1      :  1;               /*!< Select the PWM value register for the PWM_2 and PWM_3 pins pair
                                                         in complementary mode.                                                */
      __IO uint32_t  IPOL2      :  1;               /*!< Select the PWM value register for the PWM_4 and PWM_5 pins pair
                                                         in complementary mode.                                                */
      __IO uint32_t  IPOL3      :  1;               /*!< Select the PWM value register for the PWM_6 and PWM_7 pins pair
                                                         in complementary mode.                                                */
      __IO uint32_t  HALF       :  1;               /*!< Enable half-cycle reloads in Center-Aligned PWM mode                  */
      __IO uint32_t  LDFQ       :  4;               /*!< select the PWM load frequency                                         */
      __IO uint32_t  SOFTFAULT  :  1;               /*!< trigger a software fault to the PWM Fault protect mode                */
      __IO uint32_t  INIDIR     :  1;               /*!< Select initial count direction in center align mode                   */
           uint32_t             :  2;
      __IO uint32_t  TSCNT      :  2;               /*!< Trig signal output count register                                     */
      __IO uint32_t  TSSEL      :  2;               /*!< Trig signal select register                                           */
      __IO uint32_t  CH0OUTEN   :  1;               /*!< Output a signal when counter register of channel 0 equals to
                                                         VAL0                                                                  */
      __IO uint32_t  CH1OUTEN   :  1;               /*!< Output a signal when counter register of channel 1 equals to
                                                         VAL1                                                                  */
      __IO uint32_t  CH2OUTEN   :  1;               /*!< Output a signal when counter register of channel 2 equals to
                                                         VAL2                                                                  */
      __IO uint32_t  CH3OUTEN   :  1;               /*!< Output a signal when counter register of channel 3 equals to
                                                         VAL3                                                                  */
      __IO uint32_t  CH4OUTEN   :  1;               /*!< Output a signal when counter register of channel 4 equals to
                                                         VAL4                                                                  */
      __IO uint32_t  CH5OUTEN   :  1;               /*!< Output a signal when counter register of channel 5 equals to
                                                         VAL5                                                                  */
      __IO uint32_t  CH6OUTEN   :  1;               /*!< Output a signal when counter register of channel 6 equals to
                                                         VAL5                                                                  */
      __IO uint32_t  CH7OUTEN   :  1;               /*!< Output a signal when counter register of channel 5 equals to
                                                         VAL5                                                                  */
    } CTRL_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  FCTRL;                           /*!< Fault Control Register                                                */
    
    struct {
      __IO uint32_t  FMODE0     :  1;               /*!< Select automatic or manual clearing of FAULT0 pin faults              */
      __IO uint32_t  FIE0       :  1;               /*!< Enable the interrupt request generated by the PWM_FAULT0 pin          */
      __IO uint32_t  FMODE1     :  1;               /*!< Select automatic or manual clearing of Software faults                */
      __IO uint32_t  FIE1       :  1;               /*!< Enable the interrupt request generated by the Software fault          */
      __IO uint32_t  FMODE2     :  1;               /*!< Select automatic or manual clearing of ADC limit faults               */
      __IO uint32_t  FIE2       :  1;               /*!< Enable the interrupt request generated by the ADC limit fault         */
    } FCTRL_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  FLTACK;                          /*!< Fault Status/Acknowledge Register                                     */
    
    struct {
      __IO uint32_t  FTACK0     :  1;               /*!< PWM_FAULT pin error Acknowledge,Writing a Logic 1 to FTACK0
                                                         clears FFLAG0.                                                        */
      __IO uint32_t  FTACK1     :  1;               /*!< ADC limit error Acknowledge,Writing a Logic 1 to FTACK1 clears
                                                         FFLAG1.                                                               */
      __IO uint32_t  FTACK2     :  1;               /*!< Software error Acknowledge,Writing a Logic 1 to FTACK2 clears
                                                         FFLAG2                                                                */
           uint32_t             : 13;
      __IO uint32_t  FFLAG0     :  1;               /*!< PWM_FAULT pin fault flag                                              */
      __IO uint32_t  FPIN0      :  1;               /*!< PWM_FAULT pin state                                                   */
      __IO uint32_t  FLAG1      :  1;               /*!< ADC limit fault flag                                                  */
      __IO uint32_t  FPIN1      :  1;               /*!< ADC limit fault state                                                 */
      __IO uint32_t  FFLAG2     :  1;               /*!< SOFTFAULT flag                                                        */
    } FLTACK_b;                                     /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  OUTCTRL;                         /*!< Output Control Register                                               */
    
    struct {
      __IO uint32_t  OUT0       :  1;               /*!< PWM_0 control                                                         */
      __IO uint32_t  OUT1       :  1;               /*!< PWM_1 control                                                         */
      __IO uint32_t  OUT2       :  1;               /*!< PWM_2 control                                                         */
      __IO uint32_t  OUT3       :  1;               /*!< PWM_3 control                                                         */
      __IO uint32_t  OUT4       :  1;               /*!< PWM_4 control                                                         */
      __IO uint32_t  OUT5       :  1;               /*!< PWM_5 control                                                         */
      __IO uint32_t  OUT6       :  1;               /*!< PWM_6 control                                                         */
      __IO uint32_t  OUT7       :  1;               /*!< PWM_7 control                                                         */
      __IO uint32_t  OUTCTL0    :  1;               /*!< Software control enable to PWM_0                                      */
      __IO uint32_t  OUTCTL1    :  1;               /*!< Software control enable to PWM_1                                      */
      __IO uint32_t  OUTCTL2    :  1;               /*!< Software control enable to PWM_2                                      */
      __IO uint32_t  OUTCTL3    :  1;               /*!< Software control enable to PWM_3                                      */
      __IO uint32_t  OUTCTL4    :  1;               /*!< Software control enable to PWM_4                                      */
      __IO uint32_t  OUTCTL5    :  1;               /*!< Software control enable to PWM_5                                      */
      __IO uint32_t  OUTCTL6    :  1;               /*!< Software control enable to PWM_6                                      */
      __IO uint32_t  OUTCTL7    :  1;               /*!< Software control enable to PWM_7                                      */
    } OUTCTRL_b;                                    /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  CNTR;                            /*!< Counter Register                                                      */
    
    struct {
      __I  uint32_t  CNT        : 16;               /*!< 16-bit PWM counter                                                    */
    } CNTR_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CMOD;                            /*!< Counter Modulo Register                                               */
    
    struct {
      __IO uint32_t  CM         : 16;               /*!< PWM Counter Modulo value                                              */
    } CMOD_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VAL0;                            /*!< Value Register 0                                                      */
    
    struct {
      __IO uint32_t  VAL        : 16;               /*!< PWM value                                                             */
    } VAL0_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VAL1;                            /*!< Value Register 1                                                      */
    
    struct {
      __IO uint32_t  VAL        : 16;               /*!< PWM value                                                             */
    } VAL1_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VAL2;                            /*!< Value Register 2                                                      */
    
    struct {
      __IO uint32_t  VAL        : 16;               /*!< PWM value                                                             */
    } VAL2_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VAL3;                            /*!< Value Register 3                                                      */
    
    struct {
      __IO uint32_t  VAL        : 16;               /*!< PWM value                                                             */
    } VAL3_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VAL4;                            /*!< Value Register 4                                                      */
    
    struct {
      __IO uint32_t  VAL        : 16;               /*!< PWM value                                                             */
    } VAL4_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VAL5;                            /*!< Value Register 5                                                      */
    
    struct {
      __IO uint32_t  VAL        : 16;               /*!< PWM value                                                             */
    } VAL5_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VAL6;                            /*!< Value Register 6                                                      */
    
    struct {
      __IO uint32_t  VAL        : 16;               /*!< PWM value                                                             */
    } VAL6_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  VAL7;                            /*!< Value Register 7                                                      */
    
    struct {
      __IO uint32_t  VAL        : 16;               /*!< PWM value                                                             */
    } VAL7_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DTIM0;                           /*!< Deadtime Register 0                                                   */
    
    struct {
      __IO uint32_t  DTIM       : 16;               /*!< deadtime during 0 to 1 transitions                                    */
    } DTIM0_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DTIM1;                           /*!< Deadtime Register 1                                                   */
    
    struct {
      __IO uint32_t  DTIM       : 16;               /*!< deadtime during 1 to 0 transitions                                    */
    } DTIM1_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DMAP0;                           /*!< Disable Mapping Register0                                             */
    
    struct {
      __IO uint32_t  P0FLTMAP0  :  1;               /*!< Enables Fault pin 0 to protect PWM pin 0 output                       */
      __IO uint32_t  P0FLTMAP1  :  1;               /*!< Enables Software Fault to protect PWM pin 0 output                    */
      __IO uint32_t  P0FLTMAP2  :  1;               /*!< Enables ADC out of limit to protect PWM pin 0 output                  */
           uint32_t             :  5;
      __IO uint32_t  P1FLTMAP0  :  1;               /*!< Enables Fault pin 0 to protect PWM pin 1 output                       */
      __IO uint32_t  P1FLTMAP1  :  1;               /*!< Enables Software Fault to protect PWM pin 1 output                    */
      __IO uint32_t  P1FLTMAP2  :  1;               /*!< Enables ADC out of limit to protect PWM pin 1 output                  */
           uint32_t             :  5;
      __IO uint32_t  P2FLTMAP0  :  1;               /*!< Enables Fault pin 0 to protect PWM pin 2 output                       */
      __IO uint32_t  P2FLTMAP1  :  1;               /*!< Enables Software Fault to protect PWM pin 2 output                    */
      __IO uint32_t  P2FLTMAP2  :  1;               /*!< Enables ADC out of limit to protect PWM pin 2 output                  */
           uint32_t             :  5;
      __IO uint32_t  P3FLTMAP0  :  1;               /*!< Enables Fault pin 0 to protect PWM pin 3 output                       */
      __IO uint32_t  P3FLTMAP1  :  1;               /*!< Enables Software Fault to protect PWM pin 3 output                    */
      __IO uint32_t  P3FLTMAP2  :  1;               /*!< Enables ADC out of limit to protect PWM pin 3 output                  */
    } DMAP0_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  DMAP1;                           /*!< Disable Mapping Register1                                             */
    
    struct {
      __IO uint32_t  P4FLTMAP0  :  1;               /*!< Enables Fault pin 0 to protect PWM pin 4 output                       */
      __IO uint32_t  P4FLTMAP1  :  1;               /*!< Enables Software Fault to protect PWM pin 4 output                    */
      __IO uint32_t  P4FLTMAP2  :  1;               /*!< Enables ADC out of limit to protect PWM pin 4 output                  */
           uint32_t             :  5;
      __IO uint32_t  P5FLTMAP0  :  1;               /*!< Enables Fault pin 0 to protect PWM pin 5 output                       */
      __IO uint32_t  P5FLTMAP1  :  1;               /*!< Enables Software Fault to protect PWM pin 5 output                    */
      __IO uint32_t  P5FLTMAP2  :  1;               /*!< Enables ADC out of limit to protect PWM pin 5 output                  */
           uint32_t             :  5;
      __IO uint32_t  P6FLTMAP0  :  1;               /*!< Enables Fault pin 0 to protect PWM pin 6 output                       */
      __IO uint32_t  P6FLTMAP1  :  1;               /*!< Enables Software Fault to protect PWM pin 6 output                    */
      __IO uint32_t  P6FLTMAP2  :  1;               /*!< Enables ADC out of limit to protect PWM pin 6 output                  */
           uint32_t             :  5;
      __IO uint32_t  P7FLTMAP0  :  1;               /*!< Enables Fault pin 0 to protect PWM pin 7 output                       */
      __IO uint32_t  P7FLTMAP1  :  1;               /*!< Enables Software Fault to protect PWM pin 7 output                    */
      __IO uint32_t  P7FLTMAP2  :  1;               /*!< Enables ADC out of limit to protect PWM pin 7 output                  */
    } DMAP1_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CNFG;                            /*!< Configure Register                                                    */
    
    struct {
      __IO uint32_t  WP         :  1;               /*!< Enables write-protection for all write-protectable registers          */
      __IO uint32_t  NDEP01     :  1;               /*!< independent PWMs or complementary PWM pairs selection                 */
      __IO uint32_t  NDEP23     :  1;               /*!< independent PWMs or complementary PWM pairs selection                 */
      __IO uint32_t  NDEP45     :  1;               /*!< independent PWMs or complementary PWM pairs selection                 */
      __IO uint32_t  NDEP67     :  1;               /*!< independent PWMs or complementary PWM pairs selection                 */
      __IO uint32_t  BOTNEG01   :  1;               /*!< polarity for the bottom-side PWMs selection                           */
      __IO uint32_t  BOTNEG23   :  1;               /*!< polarity for the bottom-side PWMs selection                           */
      __IO uint32_t  BOTNEG45   :  1;               /*!< polarity for the bottom-side PWMs selection                           */
      __IO uint32_t  BOTNEG67   :  1;               /*!< polarity for the bottom-side PWMs selection                           */
      __IO uint32_t  TOPNEG01   :  1;               /*!< polarity for the top-side PWMs selection                              */
      __IO uint32_t  TOPNEG23   :  1;               /*!< polarity for the top-side PWMs selection                              */
      __IO uint32_t  TOPNEG45   :  1;               /*!< polarity for the top-side PWMs selection                              */
      __IO uint32_t  TOPNEG67   :  1;               /*!< polarity for the top-side PWMs selection                              */
      __IO uint32_t  EDG        :  1;               /*!< Edge-Aligned or Center-Aligned wave forms selection                   */
    } CNFG_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CCTRL;                           /*!< Channel Control Register                                              */
    
    struct {
      __IO uint32_t  SWP01      :  1;               /*!< This bit is write-protected when ENHA is zero                         */
      __IO uint32_t  SWP23      :  1;               /*!< This bit is write-protected when ENHA is zero                         */
      __IO uint32_t  SWP45      :  1;               /*!< This bit is write-protected when ENHA is zero                         */
      __IO uint32_t  SWP67      :  1;               /*!< This bit is write-protected when ENHA is zero                         */
      __IO uint32_t  VLMODE     :  2;               /*!< To be filled                                                          */
      __IO uint32_t  MSK0       :  1;               /*!< The mask of the PWM logical channel 0                                 */
      __IO uint32_t  MSK1       :  1;               /*!< The mask of the PWM logical channel 1                                 */
      __IO uint32_t  MSK2       :  1;               /*!< The mask of the PWM logical channel 2                                 */
      __IO uint32_t  MSK3       :  1;               /*!< The mask of the PWM logical channel 3                                 */
      __IO uint32_t  MSK4       :  1;               /*!< The mask of the PWM logical channel 4                                 */
      __IO uint32_t  MSK5       :  1;               /*!< The mask of the PWM logical channel 5                                 */
      __IO uint32_t  MSK6       :  1;               /*!< The mask of the PWM logical channel 6                                 */
      __IO uint32_t  MSK7       :  1;               /*!< The mask of the PWM logical channel 7                                 */
           uint32_t             :  1;
      __IO uint32_t  ENHA       :  1;               /*!< Enable Hardware Acceleration                                          */
    } CCTRL_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  PORT;                            /*!< Port Register                                                         */
    
    struct {
      __IO uint32_t  FAULTPORT  :  1;               /*!< PWM fault input value                                                 */
           uint32_t             :  7;
      __IO uint32_t  FAULTVAL0  :  1;               /*!< PWM0 output value when fault happen                                   */
      __IO uint32_t  FAULTVAL1  :  1;               /*!< PWM1 output value when fault happen                                   */
      __IO uint32_t  FAULTVAL2  :  1;               /*!< PWM2 output value when fault happen                                   */
      __IO uint32_t  FAULTVAL3  :  1;               /*!< PWM3 output value when fault happen                                   */
      __IO uint32_t  FAULTVAL4  :  1;               /*!< PWM4 output value when fault happen                                   */
      __IO uint32_t  FAULTVAL5  :  1;               /*!< PWM5 output value when fault happen                                   */
      __IO uint32_t  FAULTVAL6  :  1;               /*!< PWM6 output value when fault happen                                   */
      __IO uint32_t  FAULTVAL7  :  1;               /*!< PWM7 output value when fault happen                                   */
      __IO uint32_t  FPSEL0     :  1;               /*!< Enable PWM0 fault output FAULTVAL0                                    */
      __IO uint32_t  FPSEL1     :  1;               /*!< Enable PWM1 fault output FAULTVAL1                                    */
      __IO uint32_t  FPSEL2     :  1;               /*!< Enable PWM2 fault output FAULTVAL2                                    */
      __IO uint32_t  FPSEL3     :  1;               /*!< Enable PWM3 fault output FAULTVAL3                                    */
      __IO uint32_t  FPSEL4     :  1;               /*!< Enable PWM4 fault output FAULTVAL4                                    */
      __IO uint32_t  FPSEL5     :  1;               /*!< Enable PWM5 fault output FAULTVAL5                                    */
      __IO uint32_t  FPSEL6     :  1;               /*!< Enable PWM5 fault output FAULTVAL6                                    */
      __IO uint32_t  FPSEL7     :  1;               /*!< Enable PWM5 fault output FAULTVAL7                                    */
    } PORT_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ICCTRL;                          /*!< Internal Correction Control Register                                  */
    
    struct {
      __IO uint32_t  ICC0       :  1;               /*!< Select VAL0 or VAL1 to controls PWM0/PWM1 pair.                       */
      __IO uint32_t  ICC1       :  1;               /*!< Select VAL2 or VAL3 to controls PWM2/PWM3 pair.                       */
      __IO uint32_t  ICC2       :  1;               /*!< Select VAL4 or VAL5 to controls PWM4/PWM5 pair.                       */
      __IO uint32_t  ICC3       :  1;               /*!< Select VAL6 or VAL7 to controls PWM6/PWM7 pair.                       */
      __IO uint32_t  PAD_EN     :  1;               /*!< PWM pad output enable                                                 */
    } ICCTRL_b;                                     /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED[2];
  
  union {
    __IO uint32_t  PSCR;                            /*!< Polarity Invert control Register                                      */
    
    struct {
      __IO uint32_t  CINV0      :  1;               /*!< This bit controls the polarity of PWM compare output 0                */
      __IO uint32_t  CINV1      :  1;               /*!< This bit controls the polarity of PWM compare output 1                */
      __IO uint32_t  CINV2      :  1;               /*!< This bit controls the polarity of PWM compare output 2                */
      __IO uint32_t  CINV3      :  1;               /*!< This bit controls the polarity of PWM compare output 3                */
      __IO uint32_t  CINV4      :  1;               /*!< This bit controls the polarity of PWM compare output 4                */
      __IO uint32_t  CINV5      :  1;               /*!< This bit controls the polarity of PWM compare output 5                */
      __IO uint32_t  CINV6      :  1;               /*!< This bit controls the polarity of PWM compare output 6                */
      __IO uint32_t  CINV7      :  1;               /*!< This bit controls the polarity of PWM compare output 7                */
    } PSCR_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  CNTRINI;                         /*!< Counter Init Register                                                 */
    
    struct {
      __O  uint32_t  INITVAL    : 16;               /*!< PWM counter start value                                               */
    } CNTRINI_b;                                    /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED1;
  
  union {
    __IO uint32_t  PRESC;                           /*!< CLK Divider Register                                                  */
    
    struct {
      __IO uint32_t  PRESC      :  4;               /*!< Prescale value                                                        */
    } PRESC_b;                                      /*!< BitSize                                                               */
  };
} PWM_Type;


/* ================================================================================ */
/* ================                       DMA                      ================ */
/* ================================================================================ */


/**
  * @brief DMA module (DMA)
  */

typedef struct {                                    /*!< DMA Structure                                                         */
  
  union {
    __I  uint32_t  DMA_STATUS;                      /*!< DMA state register                                                    */
    
    struct {
      __I  uint32_t  MASTER_EN  :  1;               /*!< To be filled                                                          */
           uint32_t             :  3;
      __I  uint32_t  STATE      :  4;               /*!< To be filled                                                          */
    } DMA_STATUS_b;                                 /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  DMA_CFG;                         /*!< DMA config register                                                   */
    
    struct {
      __O  uint32_t  MASTER_EN  :  1;               /*!< To be filled                                                          */
    } DMA_CFG_b;                                    /*!< BitSize                                                               */
  };
  __IO uint32_t  CTRL_BASE_PTR;                     /*!< DMA channel control base address pointer register                     */
  __I  uint32_t  RESERVED[2];
  
  union {
    __O  uint32_t  CHNL_SW_REQUEST;                 /*!< DMA channel software request register                                 */
    
    struct {
      __O  uint32_t  DMA_SW_REQUEST: 28;            /*!< To be filled                                                          */
    } CHNL_SW_REQUEST_b;                            /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CHNL_USEBURST_SET;               /*!< DMA channel use burst set register                                    */
    
    struct {
      __IO uint32_t  DMA_USEBURST_SET: 28;          /*!< To be filled                                                          */
    } CHNL_USEBURST_SET_b;                          /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  CHNL_USEBURST_CLR;               /*!< DMA channel use burst clear register                                  */
    
    struct {
      __O  uint32_t  CHNL_USEBURST_CLR: 28;         /*!< To be filled                                                          */
    } CHNL_USEBURST_CLR_b;                          /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CHNL_REQ_MASK_SET;               /*!< DMA channel request mask set register                                 */
    
    struct {
      __IO uint32_t  CHNL_REQ_MASK_SET: 28;         /*!< To be filled                                                          */
    } CHNL_REQ_MASK_SET_b;                          /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  CHNL_REQ_MASK_CLR;               /*!< DMA channel request mask clear register                               */
    
    struct {
      __O  uint32_t  CHNL_REQ_MASK_CLR: 28;         /*!< To be filled                                                          */
    } CHNL_REQ_MASK_CLR_b;                          /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  CHNL_ENABLE_SET;                 /*!< DMA channel enable set register                                       */
    
    struct {
      __IO uint32_t  CHNL_ENABLE_SET: 28;           /*!< To be filled                                                          */
    } CHNL_ENABLE_SET_b;                            /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  CHNL_ENABLE_CLR;                 /*!< DMA channel enable clear register                                     */
    
    struct {
      __O  uint32_t  CHNL_ENABLE_CLR: 28;           /*!< To be filled                                                          */
    } CHNL_ENABLE_CLR_b;                            /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED1[2];
  
  union {
    __IO uint32_t  CHNL_PRIORITY_SET;               /*!< DMA channel priority set register                                     */
    
    struct {
      __IO uint32_t  CHNL_PRIORITY_SET: 28;         /*!< To be filled                                                          */
    } CHNL_PRIORITY_SET_b;                          /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  CHNL_PRIORITY_CLR;               /*!< DMA channel priority clear register                                   */
    
    struct {
      __O  uint32_t  CHNL_PRIORITY_CLR: 28;         /*!< To be filled                                                          */
    } CHNL_PRIORITY_CLR_b;                          /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED2[16];
  
  union {
    __IO uint32_t  CHNL_IRQ_STATUS;                 /*!< DMA interrupt state register                                          */
    
    struct {
      __IO uint32_t  CHNL_IRQ_STAT: 28;             /*!< To be filled                                                          */
    } CHNL_IRQ_STATUS_b;                            /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED3;
  
  union {
    __IO uint32_t  CHNL_IRQ_ENABLE;                 /*!< DMA interrupt enable register                                         */
    
    struct {
      __IO uint32_t  CHNL_IRQ_ENABLE: 28;           /*!< To be filled                                                          */
    } CHNL_IRQ_ENABLE_b;                            /*!< BitSize                                                               */
  };
} DMA_Type;


/* ================================================================================ */
/* ================                      ACMP                      ================ */
/* ================================================================================ */


/**
  * @brief Analog Comparator (ACMP)
  */

typedef struct {                                    /*!< ACMP Structure                                                        */
  
  union {
    __IO uint32_t  ACMP0CON;                        /*!< Analog Comparator 0 control register                                  */
    
    struct {
      __IO uint32_t  INTMODE    :  2;               /*!< interrupt mode                                                        */
      __IO uint32_t  CMPNSEL    :  3;               /*!< Select CMPIN0~7 as CMP negative input when CMPNREFEN is not
                                                         enabled                                                               */
      __IO uint32_t  CMPPSEL    :  3;               /*!< Select CMPIN0~7 as CMP positive                                       */
      __IO uint32_t  CMPNREFEN  :  1;               /*!< Enable CMPN REF as CMP negative input                                 */
      __IO uint32_t  EN         :  1;               /*!< ACMP enable                                                           */
    } ACMP0CON_b;                                   /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ACMP1CON;                        /*!< Analog Comparator 1 control register                                  */
    
    struct {
      __IO uint32_t  INTMODE    :  2;               /*!< interrupt mode                                                        */
      __IO uint32_t  CMPNSEL    :  3;               /*!< Select CMPIN0~7 as CMP negative input when CMPNREFEN is not
                                                         enabled                                                               */
      __IO uint32_t  CMPPSEL    :  3;               /*!< Select CMPIN0~7 as CMP positive                                       */
      __IO uint32_t  CMPNREFEN  :  1;               /*!< Enable CMPN REF as CMP negative input                                 */
      __IO uint32_t  EN         :  1;               /*!< ACMP enable                                                           */
    } ACMP1CON_b;                                   /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ACMPCFG;                         /*!< Comparator config register                                            */
    
    struct {
      __IO uint32_t  CMP0POLAR  :  1;               /*!< Select cmp 0 output polar.                                            */
      __IO uint32_t  CMP1POLAR  :  1;               /*!< Select cmp 1 output polar.                                            */
      __IO uint32_t  VREFLADER  :  4;               /*!< Select VDD/VREFLADER as reference                                     */
      __IO uint32_t  VREFSEL    :  1;               /*!< Select CMP VREFN                                                      */
    } ACMPCFG_b;                                    /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED;
  
  union {
    __IO uint32_t  ACMPIMSC;                        /*!< Analog Comparator interrupt mask                                      */
    
    struct {
      __IO uint32_t  ACMP0IMSC  :  1;               /*!< Analog Comparator 0 interrupt mask                                    */
      __IO uint32_t  ACMP1IMSC  :  1;               /*!< Analog Comparator 0 interrupt mask                                    */
    } ACMPIMSC_b;                                   /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ACMPRIS;                         /*!< Analog Comparator interrupt raw status                                */
    
    struct {
      __IO uint32_t  ACMP0RIS   :  1;               /*!< Analog Comparator 0 interrupt raw status                              */
      __IO uint32_t  ACMP1RIS   :  1;               /*!< Analog Comparator 0 interrupt raw status                              */
    } ACMPRIS_b;                                    /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  ACMPMIS;                         /*!< Analog Comparator masked interrupt                                    */
    
    struct {
      __IO uint32_t  ACMP0MIS   :  1;               /*!< Analog Comparator 0 masked interrupt                                  */
      __IO uint32_t  ACMP1MIS   :  1;               /*!< Analog Comparator 1 masked interrupt                                  */
    } ACMPMIS_b;                                    /*!< BitSize                                                               */
  };
} ACMP_Type;


/* ================================================================================ */
/* ================                       FMC                      ================ */
/* ================================================================================ */


/**
  * @brief Flash control block (FMC)
  */

typedef struct {                                    /*!< FMC Structure                                                         */
  __IO uint32_t  CMD;                               /*!< Flash programming command register                                    */
  __IO uint32_t  DATA;                              /*!< Flash programming data register                                       */
  __IO uint32_t  ADDR;                              /*!< Flash programming address register                                    */
  
  union {
    __IO uint32_t  FLASH_RDCYC;                     /*!< Flash read cycle register                                             */
    
    struct {
      __IO uint32_t  CYCLES     :  2;               /*!< Flash read cycle time                                                 */
    } FLASH_RDCYC_b;                                /*!< BitSize                                                               */
  };
  __IO uint32_t  FLASH_UNLOCK;                      /*!< Flash unlock Enable                                                   */
  __I  uint32_t  RESERVED[7];
  __IO uint32_t  FLASH_CHIP_ERASE;                  /*!< Flash full chip erase(not include Boot area) control                  */
  __I  uint32_t  RESERVED1[2];
  __I  uint32_t  FLASH_CFG;                         /*!< Flash size                                                            */
} FMC_Type;


/* ================================================================================ */
/* ================                       CRC                      ================ */
/* ================================================================================ */


/**
  * @brief Micro digital signal processor (CRC)
  */

typedef struct {                                    /*!< CRC Structure                                                         */
  
  union {
    __IO uint32_t  MODE;                            /*!< CRC mode register                                                     */
    
    struct {
      __IO uint32_t  CRC_POLY   :  2;               /*!< CRC polynomial                                                        */
      __IO uint32_t  BIT_RVS_WR :  1;               /*!< Data bit order                                                        */
      __IO uint32_t  CMPL_WR    :  1;               /*!< Data complement                                                       */
      __IO uint32_t  BIT_RVS_SUM:  1;               /*!< CRC sum bit order                                                     */
      __IO uint32_t  CMPL_SUM   :  1;               /*!< CRC sum complement                                                    */
      __IO uint32_t  SEED_OP    :  1;               /*!< CRC seed option set                                                   */
      __IO uint32_t  SEED_SET   :  1;               /*!< Write 1 to load seed to CRC generator                                 */
    } MODE_b;                                       /*!< BitSize                                                               */
  };
  __IO uint32_t  SEED;                              /*!< CRC seed register                                                     */
  
  union {
    __I  uint32_t  SUM;                             /*!< CRC checksum register                                                 */
    __O  uint8_t   DATA_8BIT;                       /*!< CRC data register                                                     */
  };
  
  union {
    __IO uint32_t  DMAEN;                           /*!< CRC DMA enable register                                               */
    
    struct {
      __IO uint32_t  DMAEN      :  1;               /*!< Enable DMA                                                            */
    } DMAEN_b;                                      /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  STATUS;                          /*!< CRC Status register                                                   */
    
    struct {
      __IO uint32_t  CRC_DONE   :  1;               /*!< Enable DMA                                                            */
    } STATUS_b;                                     /*!< BitSize                                                               */
  };
} CRC_Type;


/* ================================================================================ */
/* ================                       PA                       ================ */
/* ================================================================================ */


/**
  * @brief General-purpose I/Os (PA)
  */

typedef struct {                                    /*!< PA Structure                                                          */
  
  union {
    __IO uint32_t  MASK;                            /*!< Pin value mask register                                               */
    
    struct {
      __IO uint32_t  MASK0      :  1;               /*!< GPIO pin PIOn_0 access control bit                                    */
      __IO uint32_t  MASK1      :  1;               /*!< GPIO pin PIOn_1 access control bit                                    */
      __IO uint32_t  MASK2      :  1;               /*!< GPIO pin PIOn_2 access control bit                                    */
      __IO uint32_t  MASK3      :  1;               /*!< GPIO pin PIOn_3 access control bit                                    */
      __IO uint32_t  MASK4      :  1;               /*!< GPIO pin PIOn_4 access control bit                                    */
      __IO uint32_t  MASK5      :  1;               /*!< GPIO pin PIOn_5 access control bit                                    */
      __IO uint32_t  MASK6      :  1;               /*!< GPIO pin PIOn_6 access control bit                                    */
      __IO uint32_t  MASK7      :  1;               /*!< GPIO pin PIOn_7 access control bit                                    */
      __IO uint32_t  MASK8      :  1;               /*!< GPIO pin PIOn_8 access control bit                                    */
      __IO uint32_t  MASK9      :  1;               /*!< GPIO pin PIOn_9 access control bit                                    */
      __IO uint32_t  MASK10     :  1;               /*!< GPIO pin PIOn_10 access control bit                                   */
      __IO uint32_t  MASK11     :  1;               /*!< GPIO pin PIOn_11 access control bit                                   */
      __IO uint32_t  MASK12     :  1;               /*!< GPIO pin PIOn_12 access control bit                                   */
      __IO uint32_t  MASK13     :  1;               /*!< GPIO pin PIOn_13 access control bit                                   */
      __IO uint32_t  MASK14     :  1;               /*!< GPIO pin PIOn_14 access control bit                                   */
      __IO uint32_t  MASK15     :  1;               /*!< GPIO pin PIOn_15 access control bit                                   */
    } MASK_b;                                       /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  PIN;                             /*!< Pin state register                                                    */
    
    struct {
      __I  uint32_t  PIN0       :  1;               /*!< GPIO pin PIOn pin PIOn_0 PIN value                                    */
      __I  uint32_t  PIN1       :  1;               /*!< GPIO pin PIOn_1 PIN value                                             */
      __I  uint32_t  PIN2       :  1;               /*!< GPIO pin PIOn_2 PIN value                                             */
      __I  uint32_t  PIN3       :  1;               /*!< GPIO pin PIOn_3 PIN value                                             */
      __I  uint32_t  PIN4       :  1;               /*!< GPIO pin PIOn_4 PIN value                                             */
      __I  uint32_t  PIN5       :  1;               /*!< GPIO pin PIOn_5 PIN value                                             */
      __I  uint32_t  PIN6       :  1;               /*!< GPIO pin PIOn_6 PIN value                                             */
      __I  uint32_t  PIN7       :  1;               /*!< GPIO pin PIOn_7 PIN value                                             */
      __I  uint32_t  PIN8       :  1;               /*!< GPIO pin PIOn_8 PIN value                                             */
      __I  uint32_t  PIN9       :  1;               /*!< GPIO pin PIOn_9 PIN value                                             */
      __I  uint32_t  PIN10      :  1;               /*!< GPIO pin PIOn_10 PIN value                                            */
      __I  uint32_t  PIN11      :  1;               /*!< GPIO pin PIOn_11 PIN value                                            */
      __I  uint32_t  PIN12      :  1;               /*!< GPIO pin PIOn_12 PIN value                                            */
      __I  uint32_t  PIN13      :  1;               /*!< GPIO pin PIOn_13 PIN value                                            */
      __I  uint32_t  PIN14      :  1;               /*!< GPIO pin PIOn_14 PIN value                                            */
      __I  uint32_t  PIN15      :  1;               /*!< GPIO pin PIOn pin PIOn_15 PIN value                                   */
    } PIN_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  OUT;                             /*!< Pin output value register                                             */
    
    struct {
      __IO uint32_t  OUT0       :  1;               /*!< GPIO pin PIOn pin PIOn_0 output value                                 */
      __IO uint32_t  OUT1       :  1;               /*!< GPIO pin PIOn pin PIOn_1 output value                                 */
      __IO uint32_t  OUT2       :  1;               /*!< GPIO pin PIOn pin PIOn_2 output value                                 */
      __IO uint32_t  OUT3       :  1;               /*!< GPIO pin PIOn pin PIOn_3 output value                                 */
      __IO uint32_t  OUT4       :  1;               /*!< GPIO pin PIOn pin PIOn_4 output value                                 */
      __IO uint32_t  OUT5       :  1;               /*!< GPIO pin PIOn pin PIOn_5 output value                                 */
      __IO uint32_t  OUT6       :  1;               /*!< GPIO pin PIOn pin PIOn_6 output value                                 */
      __IO uint32_t  OUT7       :  1;               /*!< GPIO pin PIOn pin PIOn_7 output value                                 */
      __IO uint32_t  OUT8       :  1;               /*!< GPIO pin PIOn pin PIOn_8 output value                                 */
      __IO uint32_t  OUT9       :  1;               /*!< GPIO pin PIOn pin PIOn_9 output value                                 */
      __IO uint32_t  OUT10      :  1;               /*!< GPIO pin PIOn pin PIOn_10 output value                                */
      __IO uint32_t  OUT11      :  1;               /*!< GPIO pin PIOn pin PIOn_11 output value                                */
      __IO uint32_t  OUT12      :  1;               /*!< GPIO pin PIOn pin PIOn_12 output value                                */
      __IO uint32_t  OUT13      :  1;               /*!< GPIO pin PIOn pin PIOn_13 output value                                */
      __IO uint32_t  OUT14      :  1;               /*!< GPIO pin PIOn pin PIOn_14 output value                                */
      __IO uint32_t  OUT15      :  1;               /*!< GPIO pin PIOn pin PIOn_15 output value                                */
    } OUT_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  SET;                             /*!< Pin output value set register                                         */
    
    struct {
      __O  uint32_t  SET0       :  1;               /*!< Set GPIO pin PIOn_0 output value                                      */
      __O  uint32_t  SET1       :  1;               /*!< Set GPIO pin PIOn_1 output value                                      */
      __O  uint32_t  SET2       :  1;               /*!< Set GPIO pin PIOn_2 output value                                      */
      __O  uint32_t  SET3       :  1;               /*!< Set GPIO pin PIOn_3 output value                                      */
      __O  uint32_t  SET4       :  1;               /*!< Set GPIO pin PIOn_4 output value                                      */
      __O  uint32_t  SET5       :  1;               /*!< Set GPIO pin PIOn_5 output value                                      */
      __O  uint32_t  SET6       :  1;               /*!< Set GPIO pin PIOn_6 output value                                      */
      __O  uint32_t  SET7       :  1;               /*!< Set GPIO pin PIOn_7 output value                                      */
      __O  uint32_t  SET8       :  1;               /*!< Set GPIO pin PIOn_8 output value                                      */
      __O  uint32_t  SET9       :  1;               /*!< Set GPIO pin PIOn_9 output value                                      */
      __O  uint32_t  SET10      :  1;               /*!< Set GPIO pin PIOn_10 output value                                     */
      __O  uint32_t  SET11      :  1;               /*!< Set GPIO pin PIOn_11 output value                                     */
      __O  uint32_t  SET12      :  1;               /*!< Set GPIO pin PIOn_12 output value                                     */
      __O  uint32_t  SET13      :  1;               /*!< Set GPIO pin PIOn_13 output value                                     */
      __O  uint32_t  SET14      :  1;               /*!< Set GPIO pin PIOn_14 output value                                     */
      __O  uint32_t  SET15      :  1;               /*!< Set GPIO pin PIOn_15 output value                                     */
    } SET_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  CLR;                             /*!< Pin output value clear register                                       */
    
    struct {
      __O  uint32_t  CLR0       :  1;               /*!< Clear GPIO pin PIOn_0 output value                                    */
      __O  uint32_t  CLR1       :  1;               /*!< Clear GPIO pin PIOn_1 output value                                    */
      __O  uint32_t  CLR2       :  1;               /*!< Clear GPIO pin PIOn_2 output value                                    */
      __O  uint32_t  CLR3       :  1;               /*!< Clear GPIO pin PIOn_3 output value                                    */
      __O  uint32_t  CLR4       :  1;               /*!< Clear GPIO pin PIOn_4 output value                                    */
      __O  uint32_t  CLR5       :  1;               /*!< Clear GPIO pin PIOn_5 output value                                    */
      __O  uint32_t  CLR6       :  1;               /*!< Clear GPIO pin PIOn_6 output value                                    */
      __O  uint32_t  CLR7       :  1;               /*!< Clear GPIO pin PIOn_7 output value                                    */
      __O  uint32_t  CLR8       :  1;               /*!< Clear GPIO pin PIOn_8 output value                                    */
      __O  uint32_t  CLR9       :  1;               /*!< Clear GPIO pin PIOn_9 output value                                    */
      __O  uint32_t  CLR10      :  1;               /*!< Clear GPIO pin PIOn_10 output value                                   */
      __O  uint32_t  CLR11      :  1;               /*!< Clear GPIO pin PIOn_11 output value                                   */
      __O  uint32_t  CLR12      :  1;               /*!< Clear GPIO pin PIOn_12 output value                                   */
      __O  uint32_t  CLR13      :  1;               /*!< Clear GPIO pin PIOn_13 output value                                   */
      __O  uint32_t  CLR14      :  1;               /*!< Clear GPIO pin PIOn_14 output value                                   */
      __O  uint32_t  CLR15      :  1;               /*!< Clear GPIO pin PIOn_13 output value                                   */
    } CLR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  NOT;                             /*!< Pin output value invert register                                      */
    
    struct {
      __O  uint32_t  NOT0       :  1;               /*!< Invert GPIO pin PIOn_0 output value                                   */
      __O  uint32_t  NOT1       :  1;               /*!< Invert GPIO pin PIOn_1 output value                                   */
      __O  uint32_t  NOT2       :  1;               /*!< Invert GPIO pin PIOn_2 output value                                   */
      __O  uint32_t  NOT3       :  1;               /*!< Invert GPIO pin PIOn_3 output value                                   */
      __O  uint32_t  NOT4       :  1;               /*!< Invert GPIO pin PIOn_4 output value                                   */
      __O  uint32_t  NOT5       :  1;               /*!< Invert GPIO pin PIOn_5 output value                                   */
      __O  uint32_t  NOT6       :  1;               /*!< Invert GPIO pin PIOn_6 output value                                   */
      __O  uint32_t  NOT7       :  1;               /*!< Invert GPIO pin PIOn_7 output value                                   */
      __O  uint32_t  NOT8       :  1;               /*!< Invert GPIO pin PIOn_8 output value                                   */
      __O  uint32_t  NOT9       :  1;               /*!< Invert GPIO pin PIOn_9 output value                                   */
      __O  uint32_t  NOT10      :  1;               /*!< Invert GPIO pin PIOn_10 output value                                  */
      __O  uint32_t  NOT11      :  1;               /*!< Invert GPIO pin PIOn_11 output value                                  */
      __O  uint32_t  NOT12      :  1;               /*!< Invert GPIO pin PIOn_12 output value                                  */
      __O  uint32_t  NOT13      :  1;               /*!< Invert GPIO pin PIOn_13 output value                                  */
      __O  uint32_t  NOT14      :  1;               /*!< Invert GPIO pin PIOn_14 output value                                  */
      __O  uint32_t  NOT15      :  1;               /*!< Invert GPIO pin PIOn_15 output value                                  */
    } NOT_b;                                        /*!< BitSize                                                               */
  };
  __I  uint32_t  RESERVED[2];
  
  union {
    __IO uint32_t  DIR;                             /*!< Data direction register                                               */
    
    struct {
      __IO uint32_t  DIR0       :  1;               /*!< Selects GPIO pin PIOn_0 as input or output                            */
      __IO uint32_t  DIR1       :  1;               /*!< Selects GPIO pin PIOn_1 as input or output                            */
      __IO uint32_t  DIR2       :  1;               /*!< Selects GPIO pin PIOn_2 as input or output                            */
      __IO uint32_t  DIR3       :  1;               /*!< Selects GPIO pin PIOn_3 as input or output                            */
      __IO uint32_t  DIR4       :  1;               /*!< Selects GPIO pin PIOn_4 as input or output                            */
      __IO uint32_t  DIR5       :  1;               /*!< Selects GPIO pin PIOn_5 as input or output                            */
      __IO uint32_t  DIR6       :  1;               /*!< Selects GPIO pin PIOn_6 as input or output                            */
      __IO uint32_t  DIR7       :  1;               /*!< Selects GPIO pin PIOn_7 as input or output                            */
      __IO uint32_t  DIR8       :  1;               /*!< Selects GPIO pin PIOn_8 as input or output                            */
      __IO uint32_t  DIR9       :  1;               /*!< Selects GPIO pin PIOn_9 as input or output                            */
      __IO uint32_t  DIR10      :  1;               /*!< Selects GPIO pin PIOn_10 as input or output                           */
      __IO uint32_t  DIR11      :  1;               /*!< Selects GPIO pin PIOn_11 as input or output                           */
      __IO uint32_t  DIR12      :  1;               /*!< Selects GPIO pin PIOn_12 as input or output                           */
      __IO uint32_t  DIR13      :  1;               /*!< Selects GPIO pin PIOn_13 as input or output                           */
      __IO uint32_t  DIR14      :  1;               /*!< Selects GPIO pin PIOn_14 as input or output                           */
      __IO uint32_t  DIR15      :  1;               /*!< Selects GPIO pin PIOn_15 as input or output                           */
    } DIR_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  IS;                              /*!< interrupt sense register                                              */
    
    struct {
      __IO uint32_t  ISENSE0    :  1;               /*!< Selects interrupt on pin PIOn_0 as level or edge sensitive            */
      __IO uint32_t  ISENSE1    :  1;               /*!< Selects interrupt on pin PIOn_1 as level or edge sensitive            */
      __IO uint32_t  ISENSE2    :  1;               /*!< Selects interrupt on pin PIOn_2 as level or edge sensitive            */
      __IO uint32_t  ISENSE3    :  1;               /*!< Selects interrupt on pin PIOn_3 as level or edge sensitive            */
      __IO uint32_t  ISENSE4    :  1;               /*!< Selects interrupt on pin PIOn_4 as level or edge sensitive            */
      __IO uint32_t  ISENSE5    :  1;               /*!< Selects interrupt on pin PIOn_5 as level or edge sensitive            */
      __IO uint32_t  ISENSE6    :  1;               /*!< Selects interrupt on pin PIOn_6 as level or edge sensitive            */
      __IO uint32_t  ISENSE7    :  1;               /*!< Selects interrupt on pin PIOn_7 as level or edge sensitive            */
      __IO uint32_t  ISENSE8    :  1;               /*!< Selects interrupt on pin PIOn_8 as level or edge sensitive            */
      __IO uint32_t  ISENSE9    :  1;               /*!< Selects interrupt on pin PIOn_9 as level or edge sensitive            */
      __IO uint32_t  ISENSE10   :  1;               /*!< Selects interrupt on pin PIOn_10 as level or edge sensitive           */
      __IO uint32_t  ISENSE11   :  1;               /*!< Selects interrupt on pin PIOn_11 as level or edge sensitive           */
      __IO uint32_t  ISENSE12   :  1;               /*!< Selects interrupt on pin PIOn_12 as level or edge sensitive           */
      __IO uint32_t  ISENSE13   :  1;               /*!< Selects interrupt on pin PIOn_13 as level or edge sensitive           */
      __IO uint32_t  ISENSE14   :  1;               /*!< Selects interrupt on pin PIOn_14 as level or edge sensitive           */
      __IO uint32_t  ISENSE15   :  1;               /*!< Selects interrupt on pin PIOn_15 as level or edge sensitive           */
    } IS_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  IBE;                             /*!< Interrupt both edges register                                         */
    
    struct {
      __IO uint32_t  IBE0       :  1;               /*!< Selects interrupt on pin PIOn_0 to be triggered on both edges         */
      __IO uint32_t  IBE1       :  1;               /*!< Selects interrupt on pin PIOn_1 to be triggered on both edges         */
      __IO uint32_t  IBE2       :  1;               /*!< Selects interrupt on pin PIOn_2 to be triggered on both edges         */
      __IO uint32_t  IBE3       :  1;               /*!< Selects interrupt on pin PIOn_3 to be triggered on both edges         */
      __IO uint32_t  IBE4       :  1;               /*!< Selects interrupt on pin PIOn_4 to be triggered on both edges         */
      __IO uint32_t  IBE5       :  1;               /*!< Selects interrupt on pin PIOn_5 to be triggered on both edges         */
      __IO uint32_t  IBE6       :  1;               /*!< Selects interrupt on pin PIOn_6 to be triggered on both edges         */
      __IO uint32_t  IBE7       :  1;               /*!< Selects interrupt on pin PIOn_7 to be triggered on both edges         */
      __IO uint32_t  IBE8       :  1;               /*!< Selects interrupt on pin PIOn_8 to be triggered on both edges         */
      __IO uint32_t  IBE9       :  1;               /*!< Selects interrupt on pin PIOn_9 to be triggered on both edges         */
      __IO uint32_t  IBE10      :  1;               /*!< Selects interrupt on pin PIOn_10 to be triggered on both edges        */
      __IO uint32_t  IBE11      :  1;               /*!< Selects interrupt on pin PIOn_11 to be triggered on both edges        */
      __IO uint32_t  IBE12      :  1;               /*!< Selects interrupt on pin PIOn_12 to be triggered on both edges        */
      __IO uint32_t  IBE13      :  1;               /*!< Selects interrupt on pin PIOn_13 to be triggered on both edges        */
      __IO uint32_t  IBE14      :  1;               /*!< Selects interrupt on pin PIOn_14 to be triggered on both edges        */
      __IO uint32_t  IBE15      :  1;               /*!< Selects interrupt on pin PIOn_15 to be triggered on both edges        */
    } IBE_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  IEV;                             /*!< Interrupt event register                                              */
    
    struct {
      __IO uint32_t  IEV0       :  1;               /*!< Selects interrupt on pin PIOn_0 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV1       :  1;               /*!< Selects interrupt on pin PIOn_1 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV2       :  1;               /*!< Selects interrupt on pin PIOn_2 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV3       :  1;               /*!< Selects interrupt on pin PIOn_3 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV4       :  1;               /*!< Selects interrupt on pin PIOn_4 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV5       :  1;               /*!< Selects interrupt on pin PIOn_5 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV6       :  1;               /*!< Selects interrupt on pin PIOn_6 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV7       :  1;               /*!< Selects interrupt on pin PIOn_7 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV8       :  1;               /*!< Selects interrupt on pin PIOn_8 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV9       :  1;               /*!< Selects interrupt on pin PIOn_9 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV10      :  1;               /*!< Selects interrupt on pin PIOn_10 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV11      :  1;               /*!< Selects interrupt on pin PIOn_11 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV12      :  1;               /*!< Selects interrupt on pin PIOn_12 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV13      :  1;               /*!< Selects interrupt on pin PIOn_13 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV14      :  1;               /*!< Selects interrupt on pin PIOn_14 to be triggered rising or falling
                                                         edges.                                                                */
      __IO uint32_t  IEV15      :  1;               /*!< Selects interrupt on pin PIOn_15 to be triggered rising or falling
                                                         edges.                                                                */
    } IEV_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __IO uint32_t  IE;                              /*!< Interrupt mask register                                               */
    
    struct {
      __IO uint32_t  IE0        :  1;               /*!< Selects interrupt on pin PIOn_0 to be masked.                         */
      __IO uint32_t  IE1        :  1;               /*!< Selects interrupt on pin PIOn_1 to be masked.                         */
      __IO uint32_t  IE2        :  1;               /*!< Selects interrupt on pin PIOn_2 to be masked.                         */
      __IO uint32_t  IE3        :  1;               /*!< Selects interrupt on pin PIOn_3 to be masked.                         */
      __IO uint32_t  IE4        :  1;               /*!< Selects interrupt on pin PIOn_4 to be masked.                         */
      __IO uint32_t  IE5        :  1;               /*!< Selects interrupt on pin PIOn_5 to be masked.                         */
      __IO uint32_t  IE6        :  1;               /*!< Selects interrupt on pin PIOn_6 to be masked.                         */
      __IO uint32_t  IE7        :  1;               /*!< Selects interrupt on pin PIOn_7 to be masked.                         */
      __IO uint32_t  IE8        :  1;               /*!< Selects interrupt on pin PIOn_8 to be masked.                         */
      __IO uint32_t  IE9        :  1;               /*!< Selects interrupt on pin PIOn_9 to be masked.                         */
      __IO uint32_t  IE10       :  1;               /*!< Selects interrupt on pin PIOn_10 to be masked.                        */
      __IO uint32_t  IE11       :  1;               /*!< Selects interrupt on pin PIOn_11 to be masked.                        */
      __IO uint32_t  IE12       :  1;               /*!< Selects interrupt on pin PIOn_12 to be masked.                        */
      __IO uint32_t  IE13       :  1;               /*!< Selects interrupt on pin PIOn_13 to be masked.                        */
      __IO uint32_t  IE14       :  1;               /*!< Selects interrupt on pin PIOn_14 to be masked.                        */
      __IO uint32_t  IE15       :  1;               /*!< Selects interrupt on pin PIOn_15 to be masked.                        */
    } IE_b;                                         /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  RIS;                             /*!< Raw interrupt status register                                         */
    
    struct {
      __I  uint32_t  RIS0       :  1;               /*!< Raw interrupt status on pin PIOn_0                                    */
      __I  uint32_t  RIS1       :  1;               /*!< Raw interrupt status on pin PIOn_1                                    */
      __I  uint32_t  RIS2       :  1;               /*!< Raw interrupt status on pin PIOn_2                                    */
      __I  uint32_t  RIS3       :  1;               /*!< Raw interrupt status on pin PIOn_3                                    */
      __I  uint32_t  RIS4       :  1;               /*!< Raw interrupt status on pin PIOn_4                                    */
      __I  uint32_t  RIS5       :  1;               /*!< Raw interrupt status on pin PIOn_5                                    */
      __I  uint32_t  RIS6       :  1;               /*!< Raw interrupt status on pin PIOn_6                                    */
      __I  uint32_t  RIS7       :  1;               /*!< Raw interrupt status on pin PIOn_7                                    */
      __I  uint32_t  RIS8       :  1;               /*!< Raw interrupt status on pin PIOn_8                                    */
      __I  uint32_t  RIS9       :  1;               /*!< Raw interrupt status on pin PIOn_9                                    */
      __I  uint32_t  RIS10      :  1;               /*!< Raw interrupt status on pin PIOn_10                                   */
      __I  uint32_t  RIS11      :  1;               /*!< Raw interrupt status on pin PIOn_11                                   */
      __I  uint32_t  RIS12      :  1;               /*!< Raw interrupt status on pin PIOn_12                                   */
      __I  uint32_t  RIS13      :  1;               /*!< Raw interrupt status on pin PIOn_13                                   */
      __I  uint32_t  RIS14      :  1;               /*!< Raw interrupt status on pin PIOn_14                                   */
      __I  uint32_t  RIS15      :  1;               /*!< Raw interrupt status on pin PIOn_15                                   */
    } RIS_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __I  uint32_t  MIS;                             /*!< Masked interrupt status register                                      */
    
    struct {
      __I  uint32_t  MIS0       :  1;               /*!< Selects interrupt on pin PIOn_0 to be masked                          */
      __I  uint32_t  MIS1       :  1;               /*!< Selects interrupt on pin PIOn_1 to be masked                          */
      __I  uint32_t  MIS2       :  1;               /*!< Selects interrupt on pin PIOn_2 to be masked                          */
      __I  uint32_t  MIS3       :  1;               /*!< Selects interrupt on pin PIOn_3 to be masked                          */
      __I  uint32_t  MIS4       :  1;               /*!< Selects interrupt on pin PIOn_4 to be masked                          */
      __I  uint32_t  MIS5       :  1;               /*!< Selects interrupt on pin PIOn_5 to be masked                          */
      __I  uint32_t  MIS6       :  1;               /*!< Selects interrupt on pin PIOn_6 to be masked                          */
      __I  uint32_t  MIS7       :  1;               /*!< Selects interrupt on pin PIOn_7 to be masked                          */
      __I  uint32_t  MIS8       :  1;               /*!< Selects interrupt on pin PIOn_8 to be masked                          */
      __I  uint32_t  MIS9       :  1;               /*!< Selects interrupt on pin PIOn_9 to be masked                          */
      __I  uint32_t  MIS10      :  1;               /*!< Selects interrupt on pin PIOn_10 to be masked                         */
      __I  uint32_t  MIS11      :  1;               /*!< Selects interrupt on pin PIOn_11 to be masked                         */
      __I  uint32_t  MIS12      :  1;               /*!< Selects interrupt on pin PIOn_12 to be masked                         */
      __I  uint32_t  MIS13      :  1;               /*!< Selects interrupt on pin PIOn_13 to be masked                         */
      __I  uint32_t  MIS14      :  1;               /*!< Selects interrupt on pin PIOn_14 to be masked                         */
      __I  uint32_t  MIS15      :  1;               /*!< Selects interrupt on pin PIOn_15 to be masked                         */
    } MIS_b;                                        /*!< BitSize                                                               */
  };
  
  union {
    __O  uint32_t  IC;                              /*!< Interrupt clear register                                              */
    
    struct {
      __O  uint32_t  IC0        :  1;               /*!< Selects interrupt on pin PIOn_0 to be cleared                         */
      __O  uint32_t  IC1        :  1;               /*!< Selects interrupt on pin PIOn_1 to be cleared                         */
      __O  uint32_t  IC2        :  1;               /*!< Selects interrupt on pin PIOn_2 to be cleared                         */
      __O  uint32_t  IC3        :  1;               /*!< Selects interrupt on pin PIOn_3 to be cleared                         */
      __O  uint32_t  IC4        :  1;               /*!< Selects interrupt on pin PIOn_4 to be cleared                         */
      __O  uint32_t  IC5        :  1;               /*!< Selects interrupt on pin PIOn_5 to be cleared                         */
      __O  uint32_t  IC6        :  1;               /*!< Selects interrupt on pin PIOn_6 to be cleared                         */
      __O  uint32_t  IC7        :  1;               /*!< Selects interrupt on pin PIOn_7 to be cleared                         */
      __O  uint32_t  IC8        :  1;               /*!< Selects interrupt on pin PIOn_8 to be cleared                         */
      __O  uint32_t  IC9        :  1;               /*!< Selects interrupt on pin PIOn_9 to be cleared                         */
      __O  uint32_t  IC10       :  1;               /*!< Selects interrupt on pin PIOn_10 to be cleared                        */
      __O  uint32_t  IC11       :  1;               /*!< Selects interrupt on pin PIOn11 to be cleared                         */
      __O  uint32_t  IC12       :  1;               /*!< Selects interrupt on pin PIOn_12 to be cleared                        */
      __O  uint32_t  IC13       :  1;               /*!< Selects interrupt on pin PIOn_13 to be cleared                        */
      __O  uint32_t  IC14       :  1;               /*!< Selects interrupt on pin PIOn_14 to be cleared                        */
      __O  uint32_t  IC15       :  1;               /*!< Selects interrupt on pin PIOn_15 to be cleared                        */
    } IC_b;                                         /*!< BitSize                                                               */
  };
} PA_Type;


/* --------------------  End of section using anonymous unions  ------------------- */
#if defined(__CC_ARM)
  #pragma pop
#elif defined(__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined(__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined(__TASKING__)
  #pragma warning restore
#else
  #warning Not supported compiler type
#endif




/* ================================================================================ */
/* ================              Peripheral memory map             ================ */
/* ================================================================================ */

#define DIA_BASE                        0x1FFF0C00UL
#define SYSCON_BASE                     0x40000000UL
#define IOCON_BASE                      0x40004000UL
#define UART0_BASE                      0x40008000UL
#define UART1_BASE                      0x4000C000UL
#define UART2_BASE                      0x40010000UL
#define UART3_BASE                      0x40014000UL
#define SPI0_BASE                       0x40018000UL
#define SPI1_BASE                       0x4001C000UL
#define I2C0_BASE                       0x40020000UL
#define I2C1_BASE                       0x40024000UL
#define RTC_BASE                        0x40058000UL
#define BTIM0_BASE                      0x40028000UL
#define BTIM1_BASE                      0x4002C000UL
#define BTIM2_BASE                      0x40030000UL
#define BTIM3_BASE                      0x40034000UL
#define CTIM0_BASE                      0x40038000UL
#define CTIM1_BASE                      0x4003C000UL
#define WDT_BASE                        0x40040000UL
#define ADC_BASE                        0x40044000UL
#define PMU_BASE                        0x40048000UL
#define PWM_BASE                        0x4004C000UL
#define DMA_BASE                        0x40050000UL
#define ACMP_BASE                       0x40054000UL
#define FMC_BASE                        0x50000000UL
#define CRC_BASE                        0x50010000UL
#define PA_BASE                         0x50060000UL
#define PB_BASE                         0x50070000UL
#define PC_BASE                         0x50020000UL


/* ================================================================================ */
/* ================             Peripheral declaration             ================ */
/* ================================================================================ */

#define DIA                             ((DIA_Type                *) DIA_BASE)
#define SYSCON                          ((SYSCON_Type             *) SYSCON_BASE)
#define IOCON                           ((IOCON_Type              *) IOCON_BASE)
#define UART0                           ((UART0_Type              *) UART0_BASE)
#define UART1                           ((UART0_Type              *) UART1_BASE)
#define UART2                           ((UART0_Type              *) UART2_BASE)
#define UART3                           ((UART0_Type              *) UART3_BASE)
#define SPI0                            ((SPI0_Type               *) SPI0_BASE)
#define SPI1                            ((SPI0_Type               *) SPI1_BASE)
#define I2C0                            ((I2C0_Type               *) I2C0_BASE)
#define I2C1                            ((I2C0_Type               *) I2C1_BASE)
#define RTC                             ((RTC_Type                *) RTC_BASE)
#define BTIM0                           ((BTIM0_Type              *) BTIM0_BASE)
#define BTIM1                           ((BTIM0_Type              *) BTIM1_BASE)
#define BTIM2                           ((BTIM0_Type              *) BTIM2_BASE)
#define BTIM3                           ((BTIM0_Type              *) BTIM3_BASE)
#define CTIM0                           ((CTIM0_Type              *) CTIM0_BASE)
#define CTIM1                           ((CTIM0_Type              *) CTIM1_BASE)
#define WDT                             ((WDT_Type                *) WDT_BASE)
#define ADC                             ((ADC_Type                *) ADC_BASE)
#define PMU                             ((PMU_Type                *) PMU_BASE)
#define PWM                             ((PWM_Type                *) PWM_BASE)
#define DMA                             ((DMA_Type                *) DMA_BASE)
#define ACMP                            ((ACMP_Type               *) ACMP_BASE)
#define FMC                             ((FMC_Type                *) FMC_BASE)
#define CRC                             ((CRC_Type                *) CRC_BASE)
#define PA                              ((PA_Type                 *) PA_BASE)
#define PB                              ((PA_Type                 *) PB_BASE)
#define PC                              ((PA_Type                 *) PC_BASE)


/** @} */ /* End of group Device_Peripheral_Registers */
/** @} */ /* End of group me32g030 */
/** @} */ /* End of group (null) */

#ifdef __cplusplus
}
#endif


#endif  /* me32g030_H */

